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# Lecture 4:

Delay

1. Delay definition
2. Transient response
3. RC delay models
4. Linear delay models
1. Delay Definitions
 tpdr: rising propagation delay
– From input to rising output
crossing VDD/2
 tpdf: falling propagation delay
– From input to falling output
crossing VDD/2
 tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
 tr: rise time
– From output crossing 0.2
VDD to 0.8 VDD
 tf: fall time
– From output crossing 0.8
VDD to 0.2 VDD

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 2

1. Delay Definitions
 tcdr: rising contamination delay
– From input to rising output crossing VDD/2
 tcdf: falling contamination delay
– From input to falling output crossing VDD/2
 tcd: average contamination delay
– tpd = (tcdr + tcdf)/2

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 3

Arrival time
 Arrival time is the latest time at which each node in a block of logic
will switch
 The slack is the difference between the required and arrival times.
 Positive slack means that the circuit meets timing.
 Negative slack means that the circuit is not fast enough.

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 4

2. Transient Response
 DC analysis tells us Vout if Vin is constant
 Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
 Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 5

DC Response
 DC Response: Vout vs. Vin for a gate
 Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
VDD
– In between, Vout depends on
transistor size and current Idsp
Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 6

Transistor Operation
 Current depends on region of transistor behavior
 For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 7

Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u(t  t0 )VDD
Vin(t)
Vout (t  t0 )  VDD Vout(t)
dVout (t ) I dsn (t )
 Idsn(t)
Vin(t)

 0 t  t0

I dsn (t )   
   Vout  VDD  Vt
2
2 V DD V Vout(t)
 t
  VDD  Vt  out 2  V (t ) V  V  V
V (t )
 out t0
  
out DD t

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 8

Simulated Inverter Delay
 Solving differential equations by hand is too hard
 SPICE simulator solves the equations numerically
– Uses more accurate I-V models too!
 But simulations take time to write, may hide insight
2.0

1.5

1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5

0.0

t(s)

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 9

Delay Estimation
 We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
 The step response usually looks like a 1st order RC
response with a decaying exponential.
 Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that tpd = RC
 Characterize transistors by finding their effective R
– Depends on average current as gate switches

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 10

Effective Resistance
 Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
 Simplification: treat transistor as resistor
– Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
– R averaged across switching of digital gate
 Too inaccurate to predict current at any given time
– But good enough to predict RC delay

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 11

3. RC Delay Model
 Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 12

RC Values
 Capacitance
– C = Cg = Cs = Cd = 2 fF/mm of gate width in 0.6 mm
– Gradually decline to 1 fF/mm in nanometer techs.
 Resistance
– R  6 KW*mm in 0.6 mm process
– Improves with shorter channel lengths
 Unit transistors
– May refer to minimum contacted device (4/2 l)
– Or maybe 1 mm wide device
– Doesn’t matter as long as you are consistent

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 13

Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

d = 6RC

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 14

Delay Model Comparison

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Example: 3-input NAND
 Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).

2 2 2

3
3

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 16

3-input NAND Caps
 Annotate the 3-input NAND gate with gate and diffusion
capacitance.

2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C
9C
3 3C
5C 3C
3C
3
5C 3C
3C
3
5C 3C
3C

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 17

Elmore Delay
 ON transistors look like resistors
 Pullup or pulldown network modeled as RC ladder
 Elmore delay of RC ladder
t pd  
nodes i
Ri to sourceCi

R1 R2 R3 RN

C1 C2 C3 CN

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 18

Example: 3-input NAND
 Estimate worst-case rising and falling delay of 3-input NAND
driving h identical gates.
2 2 2 Y
3 9C 5hC
n2
3 n1 3C
h copies
3 3C

t pdr  9  5h C R   3C R   3C R  t pdf  (3C )( R3 )  (3C )( R3  R3 )  9  5h C ( R3  R3  R3 )
 15  5h RC  12  5h RC

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 19

Delay Components
 Delay has two parts
– Parasitic delay
• 15 or 12 RC
– Effort delay
• 5h RC

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 20

Contamination Delay
 Best-case (contamination) delay can be substantially less than
propagation delay.
 Ex: If all three inputs fall simultaneously

2 2 2 Y
3 9C 5hC
n2
3 n1 3C

3 3C

R  5 
tcdr   9  5h  C      3  h  RC
3  3 

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 21

Diffusion Capacitance
 We assumed contacted diffusion on every s / d.
 Good layout minimizes diffusion area
 Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too
2C 2C
Shared
Contacted
Diffusion Isolated
Contacted 2 2 2
Merged Diffusion
Uncontacted 3 7C
Diffusion 3 3C

3C 3C 3C 3 3C

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 22

Isolated/Shared/Merged Diffusion
 Shared contacted diffusion can reduce the diffusion capacitance
 Un-contacted diffusion nodes can reduce more capacitance

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 23

Layout Comparison
 Which layout is better?

VDD VDD
A B A B

Y Y

GND GND

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4. Linear delay models
 The normalized delay of a gate: d = f + p
– p is the parasitic delay
– f is the effort delay: f = gh
– g is logical effort
– h is electrical effort (fanout): h = Cout/Cin

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 25

Logical Effort
 Logical Effort is defined as the ratio of the input
capacitance of the gate to the input capacitance of
an inverter that can deliver the same output current.

## Logical effort of common gates

Gate type Number of Inputs
1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate, 2 2 2 2 2
multiplexer

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 26

Parasitic Delay
 The parasitic delay of a gate is the delay of the gate

## Parasitic delay of common gates

Gate type Number of Inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate, 2 4 6 8 2n
multiplexer

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 27

Parasitic Delay
 Parasitic Delay for n-input NAND gate

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 28

Example
 Use the linear delay model to estimate the delay of
the fanout-of-4 (FO4) inverter. Assume the inverter
is constructed in a 65 nm process with  = 3 ps.

## 5: DC and Transient Response CMOS VLSI Design 4th Ed. 29

Summary of logical Effort

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Review
1. What are tpdr, tpdf, tf, tr, tcdr, tcdf?
2. Calculate arrive time of the following circuit:

20
10 40 30
30 40
3. Explain the delay estimation of a fanout-of-1 inverter (slide 14)
4. Explain the tpdr and tpdf delay estimation of 3-input NAND
driving h identical gates (slide 19).
5. Estimate delay for the gates: AOI21, OAI31
6. What is logical effort?
7. What is parasitic delay?
8. Estimate the delay of the following gate:
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