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GENETIC ALGORITHM
Guided By: Team Members:
Dr.S.P.Joy Vasantha Rani M.Shobana(2014504610)
Asst. Professor(Sr.Gr.) W.Shalu(2014504609)
Department of Electronics Engineering
Madras Institute of Technology M.P.SatheeshKumar(2014504608)
Anna University
Chennai
OBJECTIVE
• To place CLB’s in FPGA board to reduce time
delay and wirelength using GA and GASA
algorithm
• To implement the above algorithm in VPR and
compare the result with the existing algorithm
LITERATURE REVIEW
• Yang Meng, A.E.A. Almaini,Wang Pengjun(2006). FPGA Placement
Optimization by Two-Step Unified Genetic Algorithm and Simulated
Annealing Algorithm. Journal of electronics(china) Vol.23 No.4 Pp. 632-
636 .
o GA is used to solve numerous combinational optimization problems
o GA takes too much CPU time in the late process but SA converges
faster than GA
o This paper utilizes the advantage of the global search ability of GA and
fast convergence of SA
• S. Nazeer Hussain and K. Hari Kishore(2016). Computational Optimization
of Placement and Routing using Genetic Algorithm. Indian Journal of
Science and Technology, Vol 9(47).
o This paper concentrates on solving the problems which occur in VLSI
floor planning
o It gives an overview of placement and routing problems in ICs.
o The searching for best solutions is carried out by Genetic Algorithm
(GA)
• Khushro Shahookar and Pinaki Mazumder(1990). A Genetic Approach to
Standard Cell Placement Using Meta-Genetic Parameter Optimization.
IEEE Transactions on Computer Aided Design Vol 9. No. 5 Pp 500-511
o This paper describes the implementation of the Genetic Algorithm for Standard-cell
Placement (GASP).
o The genetic algorithm applies transformations on the chromosomal(CLB) representation
of the physical layout
o Crossover, Mutation and Inversion operators are used to generate a new configuration
• Jie Cui, Xue Chen, Yongmei Lei, Weimin Xu(2010). Improving the
Efficiency of Scheduling and Placement in FPGA by Small-world Model
Based Genetic Algorithm.10th IEEE International Conference on Computer
and Information Technology(CIT)
o Genetic algorithm based on small-world model (GA-SW) is developed for solving the
scheduling and placement problem in FPGA
o A converging crossover operator is developed to prevent invalid solutions caused by
combinatorial coding
o The time complexity of GA-SW is O(n2), where n is the number of tasks
INTRODUCTION
FPGA: (Field Programmable Gate Array)
• Pre-fabricated silicon devices that can be
electrically programmed to become almost any
kind of digital circuit
• FPGAs comprise of:
• Programmable logic blocks
• Programmable routing
• I/O blocks
FLOW CHART OF FPGA DESIGN:
System Specification
Architectural Design
Functional Design
and logic design
Partitioning
Circuit Design
Floor planning
Fabrication
Packaging and
Testing
Chip
PLACEMENT
• The portion of the physical design flow that
assigns exact locations for various circuit
components within the chip’s core area
• Types of placement:
o Global placement
o Detailed pacement
• Objective:
To optimize total wire length , timing, power,
congestion , runtime minimization
VERILOG TO ROUTING(VTR)
• VTR provides open-source CAD tools for
FPGA architecture and CAD research.
• VTR enable the investigation of new FPGA
architectures and CAD algorithms, which are
not possible with closed-source tools.
• VTR include three core tools:
• ODIN II for Verilog Elaboration and front-end
hard-block synthesis
• ABC for logic synthesis
• VPR for physical synthesis and analysis
VPR (Versatile Place and Route)