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Fundamentals
Tenth Edition
Floyd
Chapter 8
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Example waveforms Summary
CLR
LOAD
D0
D1
Data
inputs D2
D3
CLK
ENP
ENT
Q0
Q1
Data
outputs Q2
Q3
RCO
12 13 14 15 0 1 2
Count Inhibit
Clear Preset
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Aynchronous Counters
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters
A 3-bit up/down counter that advances upward through
(0, 1, 2, 3, 4, 5, 6, 7) and can be reversed through the
sequence in the opposite direction (7, 6, 5, 4, 3, 2, 1,0)
UP Q0.UP
HIGH
FF0 FF1 FF2
Q2
J J1 J2
0 Q0 Q1
UP/DOWN C C C
Q0 Q1 Q2
K0 K1 K2
DOWN
Q0.DOWN
CLK
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters
• In general, most up/down counters can be reversed anywhere in the sequence.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters
• In general, most up/down counters can be reversed anywhere in the sequence.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
D0 D1 D2 D3 Data inputs
Up/Down Synchronous Counters
(15) (1) (10) (9)
74HC190
The 74HC190 is a high speed CMOS CTEN
(4) (12)
MAX/MIN
(5)
synchronous up/down decade counter D/U
(11) CTR DIV 10
with parallel load capability. LOAD (14)
CLK C
(13)
RCO
up/down input (D/U) direction of the count (3) (2) (6) (7)
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters
D0 D1 D2 D3 Data inputs
The 74HC191 has the
(15) (1) (10) (9)
same inputs and outputs 74HC191
(4) (12)
CTEN MAX/MIN
but is a synchronous D/U
(5)
(11) CTR DIV 16
up/down binary counter. LOAD (14) (13)
CLK C RCO
(3) (2) (6) (7)
Q0 Q1 Q2 Q3 Data outputs
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Synchronous Counter Design
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Synchronous Counter Design
000
100 001 Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
101 011 0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
111 010 1 0 1 1 0 0
1 0 0 0 0 0
110
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Synchronous Counter Design
Step 3: Flip-Flop Transition Table
• The J-Kpresent
For the transition table
state 101, Q0 lists
goes all
fromcombinations ofstate.
1 to 0 to the next present
• output
To make (Qthis happen, J must be a 1 and you don't care what K0 is
N) and next0 output (QN+1) on the left. The inputs
(Jproduce
that 0 = 1, K0 = X) transition are listed on the right.
that
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Synchronous Counter Design
Each time a flip-flop is clocked,
the J and K inputs required for
that transition are mapped onto
a K-map.
For the present state 000, Q0
makes a transition from 0 to 1 to the
next state. Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
Output Flip-Flop
0 0 0 0 0 1
Transitions Inputs 0 0 1 0 1 1
QN Q N+1 J K 0 1 1 0 1 0
0 0 0 X 0 1 0 1 1 0
0 1 1 X 1 1 0 1 1 1
1 0 X 1 1 1 1 1 0 1
1 1 X 0 1 0 1 1 0 0
1 0 0 0 0 0
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Complete Karnaugh Map for all 3 Flip Flops
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Synchronous Counter Design
Step 5: Logic Expression for Flip-Flop Inputs
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Synchronous Counter Design
Step 6: Counter Implementation
The logic for each input is read and the circuit is constructed.
C C C
Q0 Q1 Q2
K0 K1 K2
CLK
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Cascaded counters
Cascading is a method of achieving higher-modulus counters. For
synchronous IC counters, the next counter is enabled only when
the terminal count of the previous stage is reached.
HIGH
ƒin
Counter 1 Counter 2
16 fout ƒin
CTEN TC CTEN TC 256
CTR DIV 16 CTR DIV 16
CLK C Q0 Q1 Q2 Q3 C Q0 Q1 Q2 Q3
fin
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Counter Decoding
Decoding is the detection of a binary number and can be
done with an AND gate.
HIGH
Q2
J0 Q0 J1 Q1 J2 Q2
C C C
Q0 Q1
K0 Q0 K1 Q1 K2 Q2
CLK
1 1 1
LSB MSB
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Partial Decoding
The decade counter shown previously incorporates
partial decoding (looking at only the MSB and the
LSB) to detect 1001. This was possible because this is
the first occurrence of this combination in the sequence.
Detects 1001 by looking only at two bits
HIGH
FF0 FF1 FF2 FF3
J0 Q0 J1 Q1 J2 Q2 J3 Q3
C C C C
Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3
CLK
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Resetting the Count with a Decoder
The divide-by-60 counter in the text also uses partial
decoding to clear the tens count when a 6 was detected.
C C
CLK To next
Decode 6 counter
TC = 59
To ENABLE
Decode 59 of next CTR
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
units tens
Q0 Q2
J0 Q0 J1 Q1 J2 Q2
C C C
Q1
K0 Q0 K1 Q1 K2 Q2
CLK
1 1 1
LSB MSB
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Logic Symbols
Dependency notation allows the logical operation of a
device to be determined from its logic symbol.
Common
CTR DIV 16 control
(1) block
CLR (9)
5CT = 0
D0 D1 D2 D3 LOAD M1
(15)
M2 RCO
(3) (4) (5) (6) (10)
ENT G3
(7)
(1) ENP G4
CLR (2)
(9) CLK C5/2,3,4+
LOAD
(10) CTR DIV 16 (15)
ENT RCO (3) (14)
(7) D0 Q0
ENP 1, 5 D [1]
(2) (4) (13)
CLK C D1 [2] Q1
(5) (12)
(14) (13) (12) (11) D2 [4] Q2
(6) (11)
D3 [8] Q3
Q0 Q1 Q2 Q3
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved