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Digital

Fundamentals
Tenth Edition

Floyd

Chapter 8

© 2009 Pearson Education,©Upper


2008 Pearson Education
Floyd, Digital Fundamentals, 10th ed Saddle River, NJ 07458. All Rights Reserved
Summary
A 4-bit Synchronous Binary Counter
The 74LS163 is a 4-bit IC synchronous counter with additional features
• The counter can be synchronously preset to any 4-bit binary number
by applying the proper levels to the parallel data inputs.
 When a LOW is applied to the LOAD input, the counter will assume
the state of the data inputs on the next dock pulse
Data inputs • An active-LOW clear input (CLR) synchronously
D0 D1 D2 D3
resets all four flip-flops in the counter.
(3) (4) (5) (6)
• There are two enable inputs: ENP and ENT.
CLR (1)
(9) CTR DIV 16 These inputs must both be HIGH for the
LOAD
ENT
(10)
TC = 15
(15) counter to sequence through its binary states.
(7)
ENP
CLK
(2)
C
RCO
• The ripple clock output (RCO) goes
(14) (13) (12) (11)
HIGH when the counter reaches the last
state in its sequence of fifteen, called the
Q0 Q1 Q2 Q3
terminal count (TC = 15).
Data outputs

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Example waveforms Summary
CLR
LOAD
D0
D1
Data
inputs D2

D3

CLK
ENP
ENT

Q0
Q1
Data
outputs Q2
Q3

RCO
12 13 14 15 0 1 2

Count Inhibit
Clear Preset

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Aynchronous Counters

What kind of counter is this?


(a) Up Counter?
(b) Down Counter?
How can you make a down counter then?

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters

An up/down counter is capable of progressing in either


direction depending on a control input.
UP 1 Q0.UP
HIGH
FF0 01 FF1
Q1 Q0
1 J
01 J1
01 0 0
1 0 Q0 0 Q1
UP/DOWN C C 0 1
Q1
1 K0
Q0 0 01 K1 1 0
10
10 1 1
DOWN
Q0.DOWN
CLK
0

Up Counter Mode - Animation

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters

An up/down counter is capable of progressing in either


direction depending on a control input.
UP 0 Q0.UP
HIGH
FF0 01 FF1
Q1 Q0
1 10 01
J J1 1 1
0 0 Q0 0 Q1
UP/DOWN C C 1 0
Q1
1 K0
Q0 0 10 K1 0 1
10
10 0 0
DOWN
Q0.DOWN
CLK
1

Down Counter Mode - Animation

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters
A 3-bit up/down counter that advances upward through
(0, 1, 2, 3, 4, 5, 6, 7) and can be reversed through the
sequence in the opposite direction (7, 6, 5, 4, 3, 2, 1,0)
UP Q0.UP
HIGH
FF0 FF1 FF2
Q2
J J1 J2
0 Q0 Q1
UP/DOWN C C C
Q0 Q1 Q2
K0 K1 K2

DOWN
Q0.DOWN
CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters
• In general, most up/down counters can be reversed anywhere in the sequence.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters
• In general, most up/down counters can be reversed anywhere in the sequence.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
D0 D1 D2 D3 Data inputs
Up/Down Synchronous Counters
(15) (1) (10) (9)
74HC190
The 74HC190 is a high speed CMOS CTEN
(4) (12)
MAX/MIN
(5)
synchronous up/down decade counter D/U
(11) CTR DIV 10
with parallel load capability. LOAD (14)
CLK C
(13)
RCO

up/down input (D/U)  direction of the count (3) (2) (6) (7)

When (D/U) = HIGH  the counter counts down: Q0 Q1 Q2 Q3 Data outputs


When (D/U) = LOW  the counter counts up:
Also, this device can be preset to any desired BCD digit as deter-
mined by the states of the data inputs when the LOAD input is LOW.
The MAX/MIN output produces a HIGH pulse
- when the terminal count nine (1001) is reached in the UP mode or
- when the terminal count zero (0000) is reached in the DOWN mode.
This MAX/MIN output, along with the ripple clock output ( RCO ) and the
count enable input ( CTEN ), is used when cascading counters.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Up/Down Synchronous Counters
D0 D1 D2 D3 Data inputs
The 74HC191 has the
(15) (1) (10) (9)
same inputs and outputs 74HC191
(4) (12)
CTEN MAX/MIN
but is a synchronous D/U
(5)
(11) CTR DIV 16
up/down binary counter. LOAD (14) (13)
CLK C RCO
(3) (2) (6) (7)

Q0 Q1 Q2 Q3 Data outputs

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Synchronous Counter Design

Most requirements for synchronous counters can be met


with available ICs. In cases where a special sequence is
needed, you can apply a step-by-step design process.
The steps in design are described in detail in the text and lab manual.
Start with the desired sequence and draw a state diagram and next-
state table. The gray code sequence from the text is illustrated:
State diagram: Next state table:
000 Present State Next State
100 001 Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
101 011 0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
111 010 1 1 0 1 1 1
1 1 1 1 0 1
110 1 0 1 1 0 0
1 0 0 0 0 0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Synchronous Counter Design

Step 1: State Diagram Step 2: Next-State Table

000
100 001 Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
101 011 0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
111 010 1 0 1 1 0 0
1 0 0 0 0 0
110

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Synchronous Counter Design
Step 3: Flip-Flop Transition Table
• The J-Kpresent
For the transition table
state 101, Q0 lists
goes all
fromcombinations ofstate.
1 to 0 to the next present
• output
To make (Qthis happen, J must be a 1 and you don't care what K0 is
N) and next0 output (QN+1) on the left. The inputs
 (Jproduce
that 0 = 1, K0 = X) transition are listed on the right.
that

Output Flip-Flop Present State Next State


Transitions Inputs Q2 Q1 Q0 Q2 Q1 Q0
QN Q N+1 J K 0 0 0 0 0 1
Q Q(N+1) 0 0 1 0 1 1
00  00 0 X 0 1 1 0 1 0
0 1 0 1 1 0
00  11 1 X 1 1 0 1 1 1
11  00 X 1 1 1 1 1 0 1
11  11 X 0 1 0 1 1 0 0
1 0 0 0 0 0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Synchronous Counter Design
Each time a flip-flop is clocked,
the J and K inputs required for
that transition are mapped onto
a K-map.
For the present state 000, Q0
makes a transition from 0 to 1 to the
next state. Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
Output Flip-Flop
0 0 0 0 0 1
Transitions Inputs 0 0 1 0 1 1
QN Q N+1 J K 0 1 1 0 1 0
0 0 0 X 0 1 0 1 1 0
0 1 1 X 1 1 0 1 1 1
1 0 X 1 1 1 1 1 0 1
1 1 X 0 1 0 1 1 0 0
1 0 0 0 0 0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Complete Karnaugh Map for all 3 Flip Flops

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Synchronous Counter Design
Step 5: Logic Expression for Flip-Flop Inputs

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Synchronous Counter Design
Step 6: Counter Implementation
The logic for each input is read and the circuit is constructed.

FF0 FF1 FF2


Q2
J J1 J
0 Q0 Q1 2

C C C
Q0 Q1 Q2
K0 K1 K2

CLK

The circuit can be checked with Multisim before constructing it.


The next slide shows the Multisim result…

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Cascaded counters
Cascading is a method of achieving higher-modulus counters. For
synchronous IC counters, the next counter is enabled only when
the terminal count of the previous stage is reached.
HIGH
ƒin
Counter 1 Counter 2
16 fout ƒin
CTEN TC CTEN TC 256
CTR DIV 16 CTR DIV 16
CLK C Q0 Q1 Q2 Q3 C Q0 Q1 Q2 Q3
fin

a) What is the modulus of the cascaded DIV 16 counters?


b) If fin =100 kHz, what is fout?
a) Each counter divides the frequency by 16. Thus the
modulus is 162 = 256.
b) The output frequency is 100 kHz/256 = 391 Hz

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Counter Decoding
Decoding is the detection of a binary number and can be
done with an AND gate.
HIGH

Q2
J0 Q0 J1 Q1 J2 Q2

C C C
Q0 Q1
K0 Q0 K1 Q1 K2 Q2

CLK
1 1 1
LSB MSB

What number is decoded by


this gate?
Decoded 4
Q2Q1Q0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Partial Decoding
The decade counter shown previously incorporates
partial decoding (looking at only the MSB and the
LSB) to detect 1001. This was possible because this is
the first occurrence of this combination in the sequence.
Detects 1001 by looking only at two bits

HIGH
FF0 FF1 FF2 FF3

J0 Q0 J1 Q1 J2 Q2 J3 Q3

C C C C

Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Resetting the Count with a Decoder
The divide-by-60 counter in the text also uses partial
decoding to clear the tens count when a 6 was detected.

CLR CTR DIV 10 CLR CLR CTR DIV 6


RCO
HIGH CTEN TC = 9 CTEN

C C
CLK To next
Decode 6 counter

TC = 59
To ENABLE
Decode 59 of next CTR
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

units tens

The divide characteristic illustrated here is a good way to obtain a


lower frequency using a counter. For example, the 60 Hz power line
can be converted to 1 Hz.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Counter Decoding

Show how to decode state 5 with an active LOW output.


HIGH

Q0 Q2
J0 Q0 J1 Q1 J2 Q2

C C C

Q1
K0 Q0 K1 Q1 K2 Q2

CLK
1 1 1
LSB MSB

Notice that a NAND gate


was used to give the active
Decoded 5
LOW output.
Q2Q1Q0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Logic Symbols
Dependency notation allows the logical operation of a
device to be determined from its logic symbol.
Common
CTR DIV 16 control
(1) block
CLR (9)
5CT = 0
D0 D1 D2 D3 LOAD M1
(15)
M2 RCO
(3) (4) (5) (6) (10)
ENT G3
(7)
(1) ENP G4
CLR (2)
(9) CLK C5/2,3,4+
LOAD
(10) CTR DIV 16 (15)
ENT RCO (3) (14)
(7) D0 Q0
ENP 1, 5 D [1]
(2) (4) (13)
CLK C D1 [2] Q1
(5) (12)
(14) (13) (12) (11) D2 [4] Q2
(6) (11)
D3 [8] Q3
Q0 Q1 Q2 Q3

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

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