EE221 Lecture 32

Digital
Fundamentals
Tenth Edition
Floyd
Chapter 7
© 2009 Pearson Education,©Upper

2008 Pearson Education
Floyd, Digital Fundamentals, 10th ed Saddle River, NJ 07458. All Rights Reserved
Summary
Flip-flop Characteristics
Propagation delay time is specified for the rising and
falling outputs. It is measured between the 50% level of the
clock to the 50% level of the output transition.
50% point on triggering edge
CLK CLK 50% point
Q 50% point on LOW-to- Q 50% point on HIGH-to-

HIGH transition of Q LOW transition of Q
tPLH tPHL
The typical propagation delay time for the 74AHC family (CMOS) is
4 ns. Even faster logic is available for specialized applications.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Another propagation delay time specification is the time

required for an asynchronous input to cause a change in the
output. Again it is measured from the 50% levels. The
74AHC family has specified delay times under 5 ns.
PRE 50% point CLR 50% point
Q 50% point Q 50% point
tPLH tPHL
Summary
Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.
D
Setup time is the minimum
time for the data to be present CLK
before the clock.
Set-up time, ts
D
Hold time is the minimum time
for the data to remain after the CLK
clock.
Hold time, tH
Summary
Other specifications include

• Maximum clock frequency (fmax)
highest rate at which a flip-flop can be reliably triggered.
• Minimum pulse widths (tW) for various inputs, and
• Power dissipation.
P = Vcc × Icc
supply voltage average current
Summary
A useful comparison between logic families is the speed-power product
which is the product of the average propagation delay and the average
power dissipation. The unit is energy.
What is the speed-power product for 74AHC74? Use
the data from Table 7-5 to determine the answer.
From Table 7-5, the average propagation delay is 4.6 ns.
The quiescent power dissipated is 1.1 mW. Therefore, the
speed-power product is 5 pJ
Summary
Output
lines
Flip-flop Applications D Q0
C
Principal flip-flop R
applications are for temporary D Q1

data storage, as frequency C
dividers, and in counters R
(which are covered in detail D Q2

in Chapter 8). Parallel data
C
input lines R
Typically, for data storage Q3

D
applications, a group of flip-flops Clock C
are connected to parallel data lines

R
and clocked together. Clear
Data is stored until the next clock

pulse.
Summary
Flip-flop Applications Frequency division
For frequency division, it is simple to use a flip-flop in

the toggle mode or to chain a series of toggle flip flops to
continue to divide by two. HIGH HIGH
One flip-flop will divide fin

J QA J QB fout
by 2,
two flip-flops will divide fin CLK CLK
fin by 4 (and so on).
K K
A side benefit of frequency
fin
division is that the output
has an exact 50% duty
cycle.
Waveforms: fout
Summary
Flip-flop Applications Digital Counters
Consider negative edge-triggered J-K flip-flops.
Both flip-flops are initially RESET.
Flip-flop A toggles on the negative-going transition of each clock pulse.

The Q output of flip-flop A clocks flip-flop B,
So each time QA makes a HIGH-to-LOW transition, flip-flop B toggles.
Summary
Flip-flop Applications Digital Counters
Consider negative edge-triggered J-K flip-flops.
Both flip-flops are initially RESET.
Flip-flop A toggles on the negative-going transition of each clock pulse.

The Q output of flip-flop A clocks flip-flop B,
So each time QA makes a HIGH-to-LOW transition, flip-flop B toggles.
1. The output of a D latch will not change if
a. the output is LOW
b. Enable is not active
c. D is LOW
d. all of the above
© 2008 Pearson Education
2. The D flip-flop shown will
D Q
a. set on the next clock pulse
CLK CLK
b. reset on the next clock pulse
c. latch on the next clock pulse Q
d. toggle on the next clock pulse
3. For the J-K flip-flop shown, the number of inputs that
are asynchronous is
PRE
a. 1
b. 2 J Q
c. 3 CLK
d. 4 K Q
CLR
4. Assume the output is initially HIGH on a leading edge
triggered J-K flip flop. For the inputs shown, the output
will go from HIGH to LOW on which clock pulse?
a. 1
CLK
b. 2 J
c. 3 K
d. 4 1 2 3 4
5. The time interval illustrated is called
a. tPHL 50% point on triggering edge
b. tPLH CLK
c. set-up time
Q 50% point on LOW-to-
d. hold time HIGH transition of Q
?
6. The time interval illustrated is called
a. tPHL
b. tPLH D
c. set-up time CLK
d. hold time ?
7. The application illustrated is a
a. astable multivibrator HIGH HIGH
b. data storage device fout

J QA J QB
c. frequency multiplier
fin CLK CLK
d. frequency divider
K K
Output
lines
D Q0
8. The application illustrated is a C
a. astable multivibrator R
D Q1
b. data storage device C
c. frequency multiplier D Q2
d. frequency divider Parallel data

C
input lines R
D Q3
Clock C
R
Clear
9. A retriggerable one-shot with an active HIGH output has
a pulse width of 20 ms and is triggered from a 60 Hz line.
The output will be a
a. series of 16.7 ms pulses
b. series of 20 ms pulses
c. constant LOW
d. constant HIGH
10. The circuit illustrated is a +VCC
a. astable multivibrator
(4) (8)
R1
b. monostable multivibrator (7)
RESET VCC
DISCH
c. frequency multiplier R2 (6)
THRES OUT
(3)
(2) (5)
d. frequency divider C1
TRIG CONT
GND
(1)
Answers:
1. b 6. d
2. d 7. d
3. b 8. b
4. c 9. d
5. b 10. a

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Digital

© 2009 Pearson Education,©Upper

CLK CLK 50% point

Q 50% point on LOW-to- Q 50% point on HIGH-to-

Another propagation delay time specification is the time

PRE 50% point CLR 50% point

Q 50% point Q 50% point

Other specifications include

supply voltage average current

applications are for temporary D Q1

dividers, and in counters R

(which are covered in detail D Q2

Typically, for data storage Q3

are connected to parallel data lines

Data is stored until the next clock

For frequency division, it is simple to use a flip-flop in

One flip-flop will divide fin

Flip-flop A toggles on the negative-going transition of each clock pulse.

Flip-flop A toggles on the negative-going transition of each clock pulse.

d. toggle on the next clock pulse

c. set-up time CLK

b. data storage device fout

d. frequency divider Parallel data

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