Class D Power amplifier

-----using ADS

Song lin @utk June30

Outline
Why select Class D?
Compare different device
Simple Class D architecture
Load-pull to give out Zout
Matching and simulation results of ideal
narrow band Class D PA
Broad band matching
 Why Class D?
Class D PA works in the switching mode, with a
square wave voltage and a half wave rectified sine
wave of current.
In its ideal switching mode,
when Vds<>0, Ids=0;
when Ids<>0,Vds=0.
Class D PA can achieve very high frequency close to
100%. Although it is very nonlinear, we still can use
the LINC technique to kill the IMD product.
Two kinds of Class D PA
 Compare the device(I)
For high frequency, ----- f max the higher the better
For high on/off switching speed,----- t sd the shorter
the better
For high efficiency, the on-resistance of a switching
device must be as low as possible to minimize the
power dissipation in the switches during the positive
half cycle.----- Rs is the smaller the better.
For high Power output, ----- BV(beake down voltage)
the higher the better
For high Gain, ----- g m the bigger the better
For power dissipate,----- I ds the small the better
 Compare the device(II)
Conclusion:

Also for the wide band application, we should chose the

component whose Zout and Zin has very little variety in
some frequency range.
I suggest to use the MRF282SR1.-----N-channel
Enhancement-Mode Lateral MOSFETs
Basic Class D PA architecture
Load Pull to give out Zout
 Narrow band input and output matching
and simulation results
1.5

1.0

0.5

ts(vin), V
0.0

-0.5

-1.0

-1.5
0.0 0.5 1.0 1.5 2.0 2.5

time, nsec

ts(voad), V
2

-2

-4

-6
0.0 0.5 1.0 1.5 2.0 2.5
10 10
time, nsec
8 8
ts(ID_FET1.i), A

ts(ID_FET2.i), A
ts(vds1), V

ts(vds2), V

6 6

4 4

2 2

0 0

-2 -2
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5

time, nsec time, nsec

 Wide band matching using coaxial

freq Zin1
30.00MHz 12.879 + j1.508
80.00MHz 11.948 - j1.362
130.0MHz 10.330 - j1.846
180.0MHz 9.075 - j1.320
230.0MHz 8.380 - j0.381
A conventional design allows the coaxial 280.0MHz 8.217 + j0.612
330.0MHz 8.497 + j1.406
transformer to transform the impedance 380.0MHz 9.052 + j1.766
430.0MHz 9.545 + j1.536
to obtain a match the low end of the 480.0MHz 9.520 + j0.857
530.0MHz 8.775 + j0.239
band, then add additional low-pass 580.0MHz 7.597 + j0.117
600.0MHz 7.105 + j0.224
matching sections to lower the
impedance at the upper band edge.
Using the MRF282S to simulate narrow
band VMCD @300MHz
Push_pull structure
Narrow band matching (input, output)
Narrow band simulation results
DC Power Calculations
Power Delivered and Power-Added The exists() function checks to be sure
Efficiency Calculations the corresponding piece of data is in
the dataset. If it is not, then the
Eqn Pdel_Watts=real(0.5*vout[1]*conj(Iload.i[1])) function returns 0.

Pavs is the available source power, set on Eqn Vs_l=exists("real(Vs_low[0])")

the schematic, and passed into the dataset
using the Harmonic Balance controller. Eqn Vs_h=exists("real(Vs_high[0])")
Eqn Is_h=exists("real(Is_high.i[0])")
Eqn Pavs_Watts=10**((28-30)/10)
Eqn Is_l=exists("real(Is_low.i[0])")
Eqn PAE=100*(Pdel_Watts-Pavs_Watts)/Pdc
Eqn Pdel_dBm = 10*log10(Pdel_Watts)+30 Eqn Pdc=Is_h*Vs_h +Is_l*Vs_l +1e-20

PAE Pdel_Watts Pdc Pdel_Watts/Pdc

78.833 36.194 45.112 0.802

50 4 50 4

40 40 3

ts(ID_FET2.i), A
3
ts(ID_FET1.i), A
ts(vds2), V

30
ts(vds1), V

30 2
2
20 20
1 1
10 10

0 0 0
0

-10 -1 -10 -1

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

time, nsec time, nsec

Final schematic
Final simulation results(1)

RFfreq eta Pdc Pdel_Watts PAE Gain

0.01000 3.18477 35.42361 1.12816 -10.96363 -6.47623
0.03034 19.17149 45.42576 8.70879 8.13838 2.39960
0.05069 26.69007 41.53192 11.08490 14.62255 3.44730
0.07103 33.87357 53.37189 18.07896 24.48310 5.57170
0.09138 38.05973 50.67507 19.28679 28.16952 5.85255
0.11172 40.55221 47.00999 19.06359 29.89092 5.80199
0.13207 52.89915 57.24243 30.28076 44.14363 7.81161
0.15241 61.16288 62.92600 38.48735 53.19817 8.85313
0.17276 63.58578 59.01689 37.52635 55.09351 8.74332
0.19310 65.09090 54.75491 35.64047 55.93762 8.51940
0.21345 69.37040 53.13651 36.86101 59.93833 8.66565
0.23379 71.57224 50.51480 36.15457 61.65064 8.58163
0.25414 74.12389 49.14442 36.42776 63.92564 8.61434
0.27448 73.81647 48.24101 35.60981 63.42723 8.51572
0.29483 71.28339 45.85446 32.68661 60.35343 8.14374
0.31517 72.02632 44.49014 32.04461 60.76119 8.05760
0.33552 76.89164 44.81067 34.45566 65.70708 8.37266
0.35586 76.92763 45.92195 35.32667 66.01374 8.48109
0.37621 75.85785 47.14371 35.76221 65.22680 8.53431
0.39655 78.19259 48.25363 37.73077 67.80608 8.76702
0.41690 80.02783 47.38484 37.92106 69.45087 8.78887
0.43724 79.86804 47.11465 37.62955 69.23043 8.75535
0.45759 79.41265 46.80491 37.16902 68.70464 8.70186
0.47793 80.30537 45.77380 36.75882 69.35615 8.65366
0.49828 82.43311 43.78908 36.09670 70.98762 8.57471
0.51862 83.18813 41.57842 34.58831 71.13411 8.38932
0.53897 81.66282 40.07803 32.72885 69.15753 8.14932
0.55931 80.91020 39.06156 31.60478 68.07950 7.99753
Final simulation results(2)

60 2

1
40

ts(I_ds.i), A
0
ts(vd1), V

20 -1

-2
0
-3

-20 -4
0 1 2 3 4 5 6 7

time, nsec

eta Pdc Pdel_Watts PAE Gain

73.76255 42.70324 31.49900 62.02603 7.98301
 The problem remain:
1. The Class D PA need a resonator tank to pull out the
fundamental signal, to filter out the third time signal, so
I decide to divide the band into 3 parts, one from 30 to
88 MHz; 88MHz to 200MHz; 200MHz to 500MHz. We
can separate the signals by filter bank.
2. For the real device, the Rs isnt very small, so the
efficiency cant be so high. Because of the t ds , the Vds
and some overlap with Ids, it also kill some efficiency.
3. To achieve better performance at low frequency band, I
have to increase the Vgg.
4. ADS is very hard to converge when simulation.
Thank you!!!