Elevator Controller

Were hired to design a

digital elevator controller
for a four-floor building
1st try: Design a counter 11
that counts up and down
00, 01, 10, 11, 10, 01,
00, ... 10
Problem: Never stops!
2nd try: Add Stop button
that disables counter
01
Problem: Have to
press button when
elevator happens by
00
We need a way to have user
inputs into a complex system

Seattle Pacific University EE 1210 - Logic System Design FSM-1

 Finite State Machines
Counters - Next state based on current state
If counter is in state 101, next state is 110
No inputs (other than reset, enable)
Finite State Machines
Next state is a function of the current state and the
inputs
If the elevator is on floor 00 and the UP button is
pressed on floor 10, then move to floor 01
If current state is 00 If UP2, Next state is 01

Seattle Pacific University EE 1210 - Logic System Design FSM-2

 A Finite State Machine
Next Next floor/ Current Current floor/
direction direction
State State

State Comb.
FlipFlops Logic Outputs
For
Outputs Motor/Door
Controls
Clock
Combinational
Logic
For Next State

Example shown for

elevator controller

Elevator
Inputs Buttons

Seattle Pacific University EE 1210 - Logic System Design FSM-3

 Gumball Machine
Were building a gumball machine
15 cents for a gumball
Machine has a single slot, which can
take dimes or nickels
Subcontractor provides a coin
sensor, which has two outputs:
N is true if a nickel was input
D is true if a dime was input
We must provide the output Open
when 15 cents entered

N
Coin Candy
Gumball Open
Sensor D Machine Release
FSM Mechanism
Reset

Clk

Seattle Pacific University EE 1210 - Logic System Design FSM-4

 Gumball Machine
Reset
ND
Diagram what is going on in a state diagram
S0
Note: No
Tabulate typical input sequences: N D
ND change
ND
three nickels provided!
nickel, dime S1 S2
two nickels, dime
two dimes N D N
D
dime, nickel ND

S3 S4 S5 S6
Draw state diagram: [open=1] [open=1] [open=1]
N N N D
Inputs: N, D, reset D D
N D ND ND ND
S1 S2 S1 S2 S1 S2
Output: open S0 S0 S0
S7 S8
[open=1] [open=1]
N D N D Output (open) indicated
ND ND during states in which is
S1 S2 S1 S2
S0 S0 is asserted

Seattle Pacific University EE 1210 - Logic System Design FSM-5

 A More Efficient Solution
Q D N Q+
Current Input Input Next Q Open
State State Current Output
Reset State
0 0 0 0 0
D
0 0 1 5 0 0
ND
N ND 0 1 0 10 5 0
D 5 0 1 1 X
10 0
5 0 0 5
N 5 0 1 10 15+ 1
ND
10 5 1 0 15+
5 1 1 Output Table
X
N+D
10 0 0 10
15+ D 10 0 1 15+
[open=1]

N
10 1 0 15+
ND 10 1 1 X
Reuse states 15+ 0 0 0
whenever possible 15+ 0 1 5
15+ 1 0 10
Symbolic State Table 15+ 1 1 X

Seattle Pacific University EE 1210 - Logic System Design FSM-6

 Gumball Machine State Table
Q1 Q0 D N Q1+Q0+ Q1 Q0 Open
Encode states into binary numbers Current Input Input Next State Current Output
State State
Calculate total number of 0 0 0 0 0 0
states: 4 (0, 5, 10, 15) 0 0 0
0 0 0 1 0 1
0 0 1 0 1 0 0 1 0
Use as many bits as needed for
the states 0 0 1 1 X X 1 0 0
4 states --> 2 bits 0 1 0 0 0 1
1 1 1
0 1 0 1 1 0
Encoding: 0: 00
5: 01 0 1 1 0 1 1 Output Table
10: 10 0 1 1 1 X X
15+: 11 1 0 0 0 1 0
1 0 0 1 1 1
1 0 1 0 1 1
1 0 1 1 X X
1 1 0 0 0 0
1 1 0 1 0 1
Encoded State Table 1 1 1 0 1 0
1 1 1 1 X X

Seattle Pacific University EE 1210 - Logic System Design FSM-7

 Gumball Machine Implementation
D D
D1DN 00 01 11 10
D0DN 00 01 11 10
Q1Q0 Q1Q0 If we chose D
00 00
0 0 x 1 0 1 x 0 FFs, we dont
have to convert
01 0 1 x 1 01 1 0 x 1 Qs to FF inputs
Q0 Q0
11 0 0 x 1 11 0 1 x 0
Q1 Q1
10 1 1 x 1 10 0 1 x 1

N N

Q1 Q0 Open D1= D + NQ0Q1 + Q0Q1

Current Output
State
D2= NQ0 + NQ1Q0 + NQ1 + DQ1Q0
0 0 0
0 1 0 Open = Q1Q0
1 0 0
Note that the output is a function of only the state
1 1 1

Seattle Pacific University EE 1210 - Logic System Design FSM-8

 Inputs
FSMs change state based on clock edges
I.e. Rising clock edge clocks all FFs
State Comb. This part can
FlipFlops Logic
For change only when
Outputs
clock ticks
Clock
Combinational
Logic
For Next State Synchronous Inputs:
Change in synch with
the clock. Obey
This part can change setup and hold time.
at any time
Inputs Asynchronous
Inputs: Change at
any time. May violate
setup and hold times.

Seattle Pacific University EE 1210 - Logic System Design FSM-9

 Asynchronous vs. Synchronous Inputs
Asynchronous
Example: Elevator
pushbuttons
Arrive at any time
Usually asserted for many
clock cycles
FSM logic must not make
any assumptions about
input timing
Synchronous
Example: Data arriving on a
serial line from a computer
Arrive synchronized exactly
to a clock
One bit of data per clock
cycle
FSM can assume that data
changes once per clock
cycle

Seattle Pacific University EE 1210 - Logic System Design FSM-10

 Parity Checker
Assert output (parity) whenever input bit stream (synchronous) has odd # of 1's

Clk

Input 0 1 0 0 1 1 0 0 0 1 0

Output 0 0 1 1 1 0 1 1 1 1 0

Reset
State Q In Q+
In
Diagram Present State Input Next State
Even Q Parity
[0] Even 0 0 Even 0 Present State Output

In
Even 0 1 Odd 1 Even 0 0
In
Odd 1 0 Odd 1 Odd 1 1
Odd
[1]
Odd 1 1 Even 0 Parity = Q
In
Q+ = Q In

Seattle Pacific University EE 1210 - Logic System Design FSM-11

 Parity Checker
Q+ = Q In Parity = Q

Pre
Parity In Parity
In D Q T Q
Clr Clr
Reset Reset

D FF Implementation T FF Implementation

Parity Checking is a type of Synchronous Serial Input FSM

A single input
Input is synchronized with clock (1 bit per clock cycle)
Goal is to look for patterns in the input bit stream

Seattle Pacific University EE 1210 - Logic System Design FSM-12

 Pattern Matcher

A string recognizer has one synchronous input (X) and one

output (Z).
The output is asserted whenever the input sequence 010
has been observed, as long as the sequence 100 has never
been seen.
This is a synchronous serial Sample input/output behavior:
input problem
1. Work though sample X: 1 1 0 1 1 0 1 0 0 1 0
inputs to understand Z: 0 0 0 0 0 0 0 1 0 0 0
problem
2. Develop FSM to
recognize patterns X: 0 0 1 0 1 0 1 0 0 1 0
3. Implement using standard Z: 0 0 0 1 0 1 0 1 0 0 0
techniques

Seattle Pacific University EE 1210 - Logic System Design FSM-13

 Pattern Matcher
1. Pick a reset state.
2. Draw paths for strings to recognize (010
Reset signal places and 100)
FSM in S0 S0 Reset 3. Fill in all of the missing transitions (each
state needs a path out for 0 and 1)
[0] 1
...0 0 ...1
State S3: have recognized 010
S1 S4
if next input is 0 then have 0100 (state S6)
[0] [0] 1
0 if next input is 1 then have 0101 = 01 (state S2)
1 0
State S1: recognizes strings of form 0 (no 1 seen)
...10
S2 1 loop back to S1 if input is 0
1 S5
...01 [0] [0]
State S4: recognizes strings of form 1 (no 0 seen)
0 0 loop back to S4 if input is 1
1
S3 0 S6 ...100
State S2: if input is 1, then have 1 (state S4)
[1] [0]
0+1
...010 Outputs 1 State S5: recognizes 10
Loops in State if input is 1, then have 01 (state S2)

Seattle Pacific University EE 1210 - Logic System Design FSM-14

 Pattern Matcher - Implementation
Reset Current State Input Next State
000 S0
[0] Q2 Q1 Q0 X Q2 Q1 Q 0
0 1
0 0 0 0 0 0 1
100 0 0 0 1 1 0 0
S1 001 S4
[0] [0] 0 0 1 0 0 0 1
0 1 0 0 1 1 0 1 0
1 0 0 1 0 0 0 1 1
0 1 0 1 1 0 0
S2 1
1 S5 0 1 1 0 1 1 0
[0] [0] 101
010 0 1 1 1 0 1 0
0 1 0 1 0 0 0 1 0 1
1 0 0 1 1 0 0
S3 0 S6 110
1 0 1 0 1 1 0
[1] [0]
011 0+1 1 0 1 1 0 1 0
1 1 0 0 1 1 0
1. Assign each state a binary 1 1 0 1 1 1 0
number 1 1 1 0 X X X
2. Make the state transition table 1 1 1 1 X X X
3. Make the output table

Seattle Pacific University EE 1210 - Logic System Design FSM-15

 Pattern Matcher - Implementation
Reset Current State Output
000 S0
[0] 1
0 Q2 Q1 Q0 Z
100 0 0 0 0
S1 001 S4
0 0 1 0
[0] [0] 1
0 0 1 0 0
1 0 0 1 1 1
1 0 0 0
S2 1
1 S5 1 0 1 0
[0] [0] 101 1 1 0 0
010
0 0 1 1 1 X
1
S3 0 S6 110 Build the FSM:
[1] [0] Use three FFs
011 0+1
Build next state logic based on
state transition table
1. Assign each state a binary
number Build output logic based on
output table
2. Make the state transition table
3. Make the output table

Seattle Pacific University EE 1210 - Logic System Design FSM-16