8051 Addressing Modes

Definition & Types of Addressing Schemes

Definition : The CPU can access data in various ways,
which are called addressing modes.
Types:
1) Immediate addressing mode
2) Register addressing mode
3) Direct addressing mode
4) Register indirect addressing mode
5) Indexed addressing mode
6) Relative addressing mode
7) Absolute addressing mode
8) Long addressing mode
The source operand is a constant (specify data by its value).
The immediate data must be preceded by the pound sign, #.
can load information into any registers, including 16-bit DPTR
register.
DPTR can also be accessed as two 8-bit registers, the high byte
DPH and low byte DPL.

MOV A, #25H ;load 25H into A

MOV R4, #62 ;load 62 into R4
MOV B, #40H ;load 40H into B
MOV DPTR, #4521H ;DPTR=4521H
MOV DPL, #21H ;DPL=21H (8-bit)
MOV DPH, #45H ;DPH=45H (8-bit)
*We can also use immediate addressing mode to send data to 8051
ports.
MOV P1, #55H
 8051 has access to eight working registers (R0 to R7).
either source or destination is one of the register (R0-R7) from the
selected register bank (thro PSW).
1) ADD A, R7

The op-code is 00101111.

00101 indicates the instruction and the three lower bits, 111,
specifies the register.

2) MOV R0, A

3) MOV A, R0
The source and destination registers must match in size.
The movement of data between Rn registers is not allowed (i.e MOV
R2, R0 ; MOV R5, R7).
 specify data by its 8-bit address.
Direct addressing can access any on-chip memory location.
MOV A, 0x70 ; copy contents of RAM at 70H to A.
MOV 0xD0 ; load contents of A into PSW.
MOV P1, A ; transfers the contents of A to port 1(address
90H).
How is a variable identified if its address is
determined or modified while a program is running?
solution is indirect addressing: R0 or R1 may
operate as pointer registers (their content indicates
an address in internal RAM where data are written or
read).
In 8051 assembly language, indirect addressing is
represented by an @ before R0 or R1.

Example: MOV A, @R0

Moves a byte of data from internal RAM at
location whose address is in R0 to the accumulator.
Indexed addressing uses a base register (either the Program Counter
or data pointer (DPTR)) and an offset (the Accumulator) in forming
the effective address for a JMP or MOVC instruction.

EA = PC (or) DPTR + A

Example: MOVC A, @A+DPTR

This instruction moves a byte of data from code
memory to the accumulator. The address in code memory is found by
adding the accumulator to the data pointer.

MOV DPTR, #4000H

MOV A, #05
MOVC A, @A+DPTR ; A M[4005]
Relative addressing is used with certain jump
instructions.

Relative address (offset) is an 8-bit signed value (-128 to

127) which is added to the program counter to form the
address of next instruction. (EA = PC + (+128 or -128)).

Long range of address from 0000H to FFFFH.

Prior to addition, the program counter is incremented to

the address following the jump (the new address is relative
to the next instruction, not the address of the jump
instruction).
Absolute addressing is only used with ACALL and
AJMP.

The 11 least significant bits of the destination

address comes from the op-code and the upper five
bits are the current upper five bits in the program
counter (PC).

Op-code (1011 0110 0001 0101)

PC (1010 1110 0001 0101)
Jump address = 10101110 0001 0101
The destination is in the same 2K (211) of the
source.
Long addressing is used only with the LCALL and
LJMP instructions.
These 3-byte instructions include a full 16-bit
destination address as bytes 2 and 3 (byte1->op-
code).
The full 64K code space is available.
The instruction is long and position dependent.

Example:
LJMP, 8AF2H
- Jumps to memory location 8AF2H.