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MOKHTAR NIBOUCHE
MOKHTAR.NIBOUCHE@UWE.AC.UK
ROOM 2N36
DEPARTMENT OF ENGINEERING DESIGN AND
MATHEMATICS
FACULTY OF ENVIRONMENT AND TECHNOLOGY
UNIVERSITY OF THE WEST OF ENGLAND
Content
2
Microcontroller Vs Microprocessor.
Architecture of a microcontroller
CPU, Peripherals. I/Os. Memory
Oscillator/Clocking Signals
Watchdog timer
Etc ..
Electrically Erasable
Programmable ROM
(EEPROM)
Inputs and outputs (I/Os)
12
Microcontrollers featuring a
Harvard architecture have
two different busses. As such,
the CPU can read an
instruction and access data
memory at the same time.
One is 8 bits wide and
connects the CPU to a
memory unit (RAM).
The other bus consists of 12, 14 or 16 lines and connects the
CPU to a different memory unit (ROM).
The Harvard architecture is in general more complex
Instruction Set
23
Interrupts 14
8 input channels, 10-bit Analogue to
digital Converter (ADC)
Synchronous Serial Port (SSP) with SPI
(Master mode) and I2C (Master/Slave)
Universal Synchronous Asynchronous
Receiver Transmitter (USART/SCI)
Watchdog timer
8 Levels Stack
Direct and Indirect Addressing Modes
References/Further Reading
26