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Analog and Digital VLSI Design

EEE F313/INSTR F313

Lecture 3: Design Metrics

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Scaling
Technology shrinks by 0.7 times every generation

With every generation we can integrate 2x more

functionality

Cost of a function decreases by 2x

How to design chips with more and more functions ??

Need for Efficient Design Methodologies

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Design Abstraction
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+
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Design Metrics
Cost

Functionality and Robustness

Performance

Power and Energy Consumption

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Cost of Integrated Circuits

NRE (non-recurrent engineering) (fixed) costs

design time and effort, mask generation
one-time cost factor
Influenced by Design complexity and Designer
Productivity

= +

Recurrent costs (Variable cost)

silicon processing, packaging, test
proportional to volume
proportional to chip area
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NRE Cost is Increasing

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Die Cost

Single die

Wafer

Going up to 12 (30cm)
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Cost per Transistor

cost:
-per-transistor
1
0.1 Fabrication capital cost per transistor (Moores law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009
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Yield
cost of die + cost of die test + cost of packaging
variable cost = ----------------------------------------------------------------
final test yield

cost of wafer
cost of die = -----------------------------------
dies per wafer die yield

(wafer diameter/2)2 wafer diameter

dies per wafer = ---------------------------------- ---------------------------
die area (2 die area)1/2
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Defects

die yield = (1 + (defects per unit area die area)/)-

Depends on the complexity of process approximately 3
Defects per unit area between 0.5-1 defect/cm2

Cost = f(die area)4

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Functionality and Robustness

Functionality gets affected due to many factors

Noise unwanted variations of voltages and currents

at the logic nodes

Process variations
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Noise Sources
from two wires placed side by side
capacitive coupling
- voltage change on one wire can influence
signal on the neighboring wire
- cross talk

inductive coupling
- current change on one wire can influence
signal on the neighboring wire

from noise on the power and ground supply rails

can influence signal levels in the gate
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Thank You