COMP541

Arithmetic Circuits

Montek Singh

Mar 20, 2007

1
Topics
Adder circuits
How to subtract
Why complemented representation works out so well

Overflow

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Iterative Circuit
Like a hierachy, except functional blocks per bit

3
Adders
Great example of this type of design
Design 1-bit circuit, then expand
Lets look at
Half adder 2-bit adder, no carry in
Inputs are bits to be added
Outputs: result and possible carry
Full adder includes carry in, really a 3-bit adder

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Half Adder
S = X Y
C = XY

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Full Adder
Three inputs. Third is Cin
Two outputs: sum and carry

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Two Half Adders (and an OR)

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Ripple-Carry Adder

Straightforward connect full adders

Carry-out to carry-in chain
C0 in case this is part of larger chain, or just 0

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Hierarchical 4-Bit Adder
We can easily use hierarchy here
Design half adder
Use in full adder
Use full adder in 4-bit adder

Verilog code in textbook

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Behavioral Verilog
// 4-bit Adder: Behavioral Verilog

module adder_4_b_v(A, B, C0, S, C4);

input[3:0] A, B;
input C0;
output[3:0] S;
output C4; Addition (unsigned)

assign {C4, S} = A + B + C0;

endmodule
Concatenation operation

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Whats Problem with Design?

Delay
Approx how much?
Imagine a 64-bit adder
Look at carry chain

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Carry Lookahead Adder
Note that add itself just 2 level

Idea is to separate carry from adder function

Then make carry approx 2-level all way across larger adder

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Four-bit Ripple Carry
Reference

Adder function
separated from
carry

Notice adder has A, B, C in

and S out, as well as G,P out.

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Propagate
The P signal is called propagate
P = A B
Means to propagate incoming carry

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What Does This Mean?
No Carry Here
So the propagate signal indicates that condition of
incoming should pass on

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Generate
The G is generate
Its G = AB, so new carry created
So its ORed with incoming carry

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Said Differently
If A B and theres incoming carry, carry will be
propagated
And S will be 0, of course

If AB, then will create carry

Incoming will determine whether S is 0 or 1

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Ripple Carry Delay: 8 Gates

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Turn Into Two Gate Delays

Design changed from deep (in delay) to wide

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C1 Just Like Ripple Carry

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C2 Circuit Two Levels

G from before and P to pass on This checks two propagates and a carry in

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C3 Circuit Two Levels

Generate from
level 0 and two
propagates

G from before and P to pass on

This checks three propagates and a carry in

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What Happens as Scale Up?

Can I realistically make 64-bit adder like this?

Have to AND 63 propagates and Cin!
Compromise
Hierarchical design
More levels of gates

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Making 4-Bit Adder Module

Create propagate and generate signals for whole

module

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Group Propagate

Make propagate of whole 4-bit block

P0-3 = P3P2P1P0

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Group Generate

Does G created upstream pass on because of string of Ps

(also G3)?
Indicates carry generated in block

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Hierarchical Carry

A B A B
4-bit adder 4-bit adder
S G P Cin S G P Cin

C8 C4

Look Ahead C0

Left lookahead block is exercise for you

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Practical Matters
FPGAs like ours have limited inputs per block
Instead they have special circuits to make adders
So dont expect to see same results as theory would
suggest

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On to Subtraction
First, look at unsigned numbers
Motivates why we typically use complemented representation

Then look at 2s complement

Imagine a subtractor circuit (next)

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One-bit Subtractor
Inputs: Borrow in, minuend and subtrahend
Review: subtrahend is subtracted from minuend
Outputs: Difference, borrow out
Could use like adder
One per bit

M S
Bout 1-bit sub Bin
D

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Example

If no borrow, then result is

non-negative (minuend >=
subtrahend).
Borrow 1 0 0

Minuend 0 1 1 Since there is borrow, result

must be negative.
Subtrahend 1 1 0
Difference 1 0 1 The magnitude must be
corrected.
Correct Diff - 0 1 1
Next slide.

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Correcting Result

What, mathematically, does it mean to

borrow?
If borrowing at digit i-1 you are adding 2i
Next Slide

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Correcting Result 2
If M is minuend and N subtrahend of numbers length
n, difference was
2n + M N
What we want is magnitude of N-M (with minus sign
in front)
Can get by subtracting previous result from 2n
N - M = 2n (M N + 2n)

This is called
2s complement

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Put Another Way
This is equivalent to how we do subtraction in our
heads
Decide which is greater
Swap if necessary
Subtract

Could build a circuit this way

Or just look at borrow bit

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Algorithm
1. Subtract N from M
2. If no borrow, then M N and result is OK
3. Otherwise, N > M so result must be subtracted
from 2n (and minus sign prepended)

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Pretty Expensive Hardware!

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That Complex Design not Used
Thats why people use complemented interpretation
for numbers
2s complement
1s complement

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1s Complement

Given: binary number N with n digits

1s complement defined as
(2n 1) - N

2n - 1 1 1 1 1 1 1 1

-N 1 0 1 1 0 0 1

1s Compl. 0 1 0 0 1 1 0

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2s Complement

Given: binary number N with n digits

2s complement defined as
2n N for N 0
0 for N = 0
Exception is so result will always have n bits

2s complement is just a 1 added to 1s

complement

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Important Property
Complement of a complement generates original
number

NOTE: We havent talked about negative numbers

yet. Still looking at unsigned

Lets look at new design for subtractor

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New Algorithm for M-N

1. Add 2s complement of N to M
This is M + (2n N) = M N + 2n
2. If M N, will generate carry (why?)
Discard carry
Result is positive M - N
3. If M < N, no end carry (why?)
Take 2s complement of result
Place minus sign in front

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Example
X = 101_0100 minus Y = 100_0011

X 1 0 1 0 1 0 0
+ 2s comp Y 0 1 1 1 1 0 1
Sum 1 0 0 1 0 0 0 1

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Example 2
Y = 100_0011 minus X = 101_0100

Y 1 0 0 0 0 1 1
+ 2s comp X 0 1 0 1 1 0 0
Sum 1 1 0 1 1 1 1

No end carry
Answer: - (2s complement of Sum)
- 0010001

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Adder-Subtractor
Need only adder and complementer for input to
subtract

Need selective complementer to make negative

output back from 2s complement
Or go through adder again. See next slide

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Design of Adder/Subtractor

S low for add,

high for subtract

Inverts each bit

of B if S is 1

Adds 1 to
make 2s
complement

Output is 2s complement if B > A

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Signed Arithmetic
Review characteristics of signed representations

Signed magnitude
Left bit is sign, 0 positive, 1 negative
Other bits are number
2s complement
1s complement

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Observations

1s C and Signed Mag

have two zeros
2s C has more
negative than
positive
All negative numbers
have 1 in high-order

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Advantages/Disadvantages
Signed magnitude has problem that we need to
correct after subtraction
Ones complement has a positive and negative zero
Twos complement is most popular
Arithmetic operations easy

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Conclusion: 2s Complement
Addition easy on any combination of positive and
negative numbers
To subtract
Take 2s complement of subtrahend
Add
This performs A + ( -B), same as A B

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Overflow
Two cases of overflow for addition of signed numbers
Two large positive numbers overflow into sign bit
Not enough room for result
Two large negative numbers added
Same not enough bits
Carry out can be OK

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Examples
4-bit signed numbers
7 + 7
7 7
Generates carry but result OK

-7 -7
4 + 4
Generates no Cout, but overflowed

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Overflow Detection
Condition is that either Cn-1 or Cn is high, but not
both

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