Professional Documents
Culture Documents
Inverter
1
Outline
2
Q&A
3
Q&A
4
CMOS Inverter Static Behavior:
DC Analysis
5
CMOS Inverter: DC Analysis
7
nMOS and pMOS operation
VDD VDD
Idsp Idsp
Vin Vout Vin Vout
Idsn Idsn
9
Graphical derivation of the inverter DC
response: current vs. Vout, Vin
Load Line Analysis:
For a given Vin:
Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal
10
Graphical derivation of the inverter DC
response: Load Line Analysis
Vin = 0
Vin0
Idsn, |Idsp|
Vin0
VDD
Vout
11
Graphical derivation of the inverter DC
response: Load Line Analysis
Vin = 0.2 VDD
Vin1
Idsn, |Idsp|
Vin1
VDD
Vout
12
Graphical derivation of the inverter DC
response: Load Line Analysis
Idsn, |Idsp|
Vin2
Vin2
VDD
Vout
13
Graphical derivation of the inverter DC
response: Load Line Analysis
Idsn, |Idsp|
Vin3
Vin3
VDD
Vout
14
Graphical derivation of the inverter DC
response: Load Line Analysis
Vin4
Idsn, |Idsp|
Vin4
VDD
Vout
15
Graphical derivation of the inverter DC
response: Load Line Analysis
Vin = VDD
Vin0 Vin5
Vin1
Idsn, |Idsp|
Vin2
Vin3
Vin4
VDD
Vout
16
DC Transfer Curve
Transcribe points onto Vin vs. Vout plot
17
DC transfer curve: operating regions
18
Beta Ratio
If bp / bn 1, switching point will move from VDD/2
Called skewed gate
19
Noise Margins
How much noise can a gate input see before it does not
recognize the input ?
20
Noise Margins
To maximize noise margins, select logic levels at unity gain
point of DC transfer characteristic
21
DC parameters
Input switching threshold: VTH
Minimum high output voltage: VOH
Maximum low output voltage: VOL
Minimum HIGH input voltage: VIH
Maximum LOW input voltage: VIL
22
CMOS Inverter Dynamic Behavior:
AC Analysis
23
CMOS Inverter Dynamic Behavior:
AC Analysis
The switching characteristic (Vout(t) given Vin(t)) of a logic gate
tells the speed at which the gate can operate
The switching speed of a logic gate can be measured in terms of
the time required to charge and discharge a capacitive load
Critical paths
Timing Analyzers automatically finds the slowest paths in a logic
design
Critical paths can be affected at various levels:
Architecture/ Microarchitecture Level
Logic Level
Circuit Level
Layout level
24
Inverter Step Response
tr, tf
Tells how steep can be the waveform that the
logic gate is able to provide at its output
tpdr, tpdf
Input-to-output delay of the logic gate (time
needed for the output to respond to a change
in the input)
27
Factors affecting delay
28
Simulated Inverter Delay
Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
Uses more accurate I-V models too!
But simulations take time to write
It is important to develop back of the envelope techniques to rapidly
estimate delay, understand its origin, and figure out how it can be
reduced
2.0
1.5
1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5
0.0
29
0.0 200p 400p 600p 800p 1n
t(s)
Delay Estimation
We would like to be able to easily estimate delay
Not as accurate as simulation
But easier to ask What if ?
The step response usually looks like a 1st order RC
response with a decaying exponential.
Use RC delay models to estimate delay
C = total capacitance on output node
Use effective resistance R
So that tpd = RC
Characterize transistors by finding their effective R
Depends on average current as gate switches
30
RC Delay Models
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d
31
Power Dissipation
32
Power Dissipation
Dynamic Dissipation
Charging and discharging (switching) of the load capacitance
Short-Circuit current while both pMOS and nMOS networks
are partially ON
33
Static Dissipation Pstatic VDD I leakage
34
Dynamic Dissipation
T T
1 VDD
Pdynamic Psw Psc i DD (t) VDDdt i DD (t)dt
T0 T 0
Assuming a logic gate goes through one complete charge/discharge cycle
every clock cycle:
Psw C VDD
2
f clock
Because most gates do not switch every clock cycle, we introduce a corrective
activity factor a:
Psw C VDD
2
f clock
A clock has a=1 because it rises and fall every cycle, but most data have a
maximum activity factor a=0.5 because they transition only once every cycle 35
Dynamic Dissipation
36
Low Power Design
37
Dynamic Power Reduction
39
Static Power Reduction cont.