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A Second Order Bang-Bang Digital Phase

Locked Loop with Output Signal Generated


via Frequency Transformation

PhD candidate Alwaled Alzarok Alsharef P46991


Supervisor Prof. Dr. Mohd. Alauddin Mohd. Ali
Co-supervisor Hilmi Sanusi
Outline

Introduction
Problem Statement
Objectives and Scope
Literature Review
General Methodology
The Proposed Oscillator
High-Level Validation
Modeling in Verilog
Implementation on FPGA
Summary of Contributions
Conclusions and future workand Future Work
Introduction

Timing information is crucial to guarantee consistent operation of


synchronized systems.
Phase Looked Loop (PLL) device is commonly used to obtain timing
information.
Digital Phase looked loop (DPLL) systems have advantages over the analog
phase looked loop systems in terms of low power operation, less sensitive
to process, voltage, and temperature. Thus, it is the preferable alternative
for analog PLL systems.
Bang-Bang DPLL (BBDPLL) is an emerging technology that operates at
higher frequency and is commonly utilized in clock and data recovery in
communication systems.
Frequency multiplication arises in the conventional DPLL and limits the
operating frequency of the DPLL. Thus, frequency transformation
controlling technique in BBDPLL is explored in this work to design BBDPLL
that is able to work at high operating frequencies and eliminate the
frequency multiplication in the conventional BBDPLL architecture.
Problem Statement
The increasing demand for faster data transmission requires a high-speed receiver.
The latest trend in the digital PLL is the principle of digital correction of the phase or
frequency. In this case, to ensure high accuracy, the frequency of the local oscillator
(LO) in the system, as well as other functional blocks, must work on frequencies that
are much higher than the input frequency, which is usually implemented through
the idea of frequency multiplication. In the case of high input frequency, such
relationship is limited by the characteristics of digital elements and frequency
multiplication in such situation is no more an option in the limits of current
technology.
Problem Statement

The two main problems in DPLL as a synchronization system are the high
operation frequencies and the requirement of low phase noise performance.

A possible solution to work around the problems of frequency multiplication is


to use other techniques in order to maintain the accuracy of DPLL output
frequency in synchronization systems.

A second challenge is how to employ the digital control method with the
Digital Controlled LC Oscillator (DCLCO) that is characterized by a high Q
performance.

Another challenge to improve the speed of DPLL is to improve the design of


the phase detector. Several researchers have developed the bang-bang phase
detector as it works in high frequencies. That detector is the target of this
thesis in particular.
Objectives and Scope

To propose a modified DPLL based on frequency


transformation method in order to increase the operating
frequency.

To develop a mathematical model for the proposed DPLL,


validate the model and analyze its quality;

To implement the proposed DPLL design using FPGA and


validate this implementation .
Literature Review
Author Objective Phase Detector Oscillator type Constraints
Ryu et al. 2013 recognizes a peaking-free jitter TDC was An LC-DCO was also utilized in this Input / output frequency multiplication
transfer implemented using a design
three BPFD

Lee et al. 2013 accomplish low phase noise and low a bang-bang phase CRs: providing relaying service to PUs. Input / output frequency multiplication
power at the same time detector PUs: selecting best relaying services

Lin 2000 This design is aimed to achieve 210 Bidders (CRs) employs a DCO that comprises an LC Input / output frequency multiplication
ps peak to peak jitter oscillator with digital and tunable
varactor banks.

Salvatore et al. an ADPLL for wireless applications Input / output frequency multiplication
2009 in the WiMAX DLL based TDC DCO is consisting in the LC tank
with BBPD

Staszewski et al. a single-chip GSM/EDGE transceiver LC oscillator as the DCO Input / output frequency multiplication
2005
TDC
Helal et al. (2008) clock multiplier Input / output frequency multiplication
TDC (time to digital Ring Oscillator
converter)

Tierno et al. (2008) frequency synthesizer for RF wireless Input / output frequency multiplication
a BBPFD 3-stages static inverter based ring
oscillator
General Methodology
The Proposed Oscillator

Injection LC
Oscillator 1

DPLL Output
OR
Gate
Local Oscillator
Phase Controller Divider

Injection LC
Remove Pulse Add Pulse Oscillator 2
The Proposed Oscillator

VIN

VOUT

Timing diagram of synchronization and injection oscillator signals


The Proposed Oscillator

The relationship between the reference signal and the injection


oscillator is determined by the following equation:

n
f LO f IO
n 1
The Proposed Oscillator

Control period

Synchronization period

TC nt LO ( n 1 )t IO
1 1 2
TC ( n 1 )t LO nt IO t IO t t IO
n n n

1 1 2
TC ( n 1 )t LO ( n 2 )t IO t IO
n t t IO
n n
The Proposed Oscillator

2.00E-03
1.89E-03
1.80E-03

1.60E-03
frequency instability

1.40E-03

1.20E-03

1.00E-03
9.25E-04
8.00E-04

6.00E-04

4.00E-04

2.00E-04 1.98E-04

0.00E+00 3.04E-05
0 50 100 150 200 250 300
divider coefficient

Relationship between coefficient of the divider and frequency


instability of injection oscillator

Stability Requirements for the Oscillator


The Proposed Oscillator

The transfer function of the counter-divider with respect to the input of


correction impulse is given by:

r
W( S )
1 TC S

A second-order digital phase locked loop system

MATHEMATICAL MODEL
The Proposed Oscillator
Transfer function of the System kr( ST 1)
H (S ) .
3 2
S T C S T pkrT kr

Stability of the System


S 3T T S 2T SKrT Kr
u C u u
Tu Kr( Tu TC ) 0
Tu TC

The error transfer function is

S 2T (1 S C )
d lim SH ( S ) ( S )
H (S ) .
S 2 (1 S C ) k r( ST 1) S 0

2 T
( S ) 2 / S 3 ( S )
kr
Therefore, this type of PLL can trace a frequency ramp and therefore can be
used in the timing recovery and in space and satellite device

MATHEMATICAL MODEL
The Proposed Oscillator

Proportional
path

Incoming
signal Ring
Phase Code adder oscillator or
detector
LC tank
output
signal
Integral
path

divider

Conventional DPLL without the Proposed Oscillator


The Proposed Oscillator

Local
Oscillator

+ Add-Remove Injected LC
Divider
Incoming signal Pluse oscillator
Phase Averaging -
detector Device
- +

Transformer code into


output signal frequency

Integral path

DPLL with the Proposed Oscillator


High Level Validation
High Level Validation

Simulation result of second order Input / Output


High Level Validation

The value of overshoot is 78%, the number of oscillations in the period of control is
equal to 6. The setting time of the transition process is 0.00095s, the rising time is
3.4695e-006s, the Peak is 1.7759, and the Peak Time is 8.9127e-006 s.

Transition Response of 2nd Order DPLL


High Level Validation

These characteristics show that the simulated system is stable and has a margin
of stability in phase equal to 24.6, which corresponds to the requirements of
sustainability.

Body Diagram of 2nd Order DPLL


Modeling in Verilog

Phase Detector Modeled in Verilog


Modeling in Verilog

GLS for Averaging Device


Modeling in Verilog

GLS for Ideal Integrator Device


Modeling in Verilog

Phase Controller
Modeling in Verilog

Pulse Output Direct Frequency Synthesizer


Implementation on FPGA

Phase Detector
Implementation on FPGA

UP-Down Counter
Implementation on FPGA

Ideal Integrator
Implementation on FPGA

Digital Phase Controller with Adding Pulse


Implementation on FPGA

Digital Phase Controller with Removing Pulse


Implementation on FPGA

Measure Output of Proposed DPLL


Implementation on FPGA

Prototype of the Proposed Design


Implementation on FPGA
Summary of Contributions

A new structure of a Bang- Bang Digital Phase Locked Loop BBDPLL is built.

Formulating a novel mathematical model for the new structure of (BBDPLL).

Building a novel digital controlled LC oscillator based on the method of


frequency transformation.

Development of a simple and accurate new pulse output direct digital


synthesizer to avoid the use of DAC.

Development of a simple and accurate digital proportional integral controller


PI (acts as a digital filter).

Development of a simple and accurate digital Bang-Bang phase detector.


Conclusions and Future Work

The conventional digital PLL was modified in order to increase the operating
frequency.

A mathematical model of the proposed (DPLL) based on frequency


transformation method was developed.

The implementation of the proposed design is performed.

One significant improvement is to implement the DPLL in the current CMOS


technology.

One other possible development would be to make the frequency divider


synchronous in order to be faster.

Another improvement would be to implement the gain by the use of artificial


intelligence methods such as a fuzzy lookup table.
List of Publications

AA Alsharef, MAM Ali, H Sanusi. 2012. Direct Digital Frequency Synthesizer


Simulation and Design by means of Quartus-M0delSim. Journal of Applied
Sciences, 12(20): 2172-2177.

AA Alsharef, MAM Ali, H Sanusi. Direct Digital Frequency Synthesizer Design and
Implementation on FPGA Research Journal of Applied Sciences Year: 2012 |
Volume: 7 | Issue: 8 | Page No.: 387-390.

AA Alsharef, Marvast, M. T., Ali, M. M., & Sanusi, H. 2011. A high speed and low
power voltage controlled ring oscillator for phase locked loop circuits. Proceedings
of the Micro and Nanoelectronics (RSM), 2011 IEEE Regional Symposium on, pp.
132-134.
AA Alsharef, MAM Ali, H Sanusi A Digital Controlled LC Oscillator with Output
Signal Generated via Frequency Transformation for High Speed Digital PLL (
preparing and writing)

AA Alsharef, MAM Ali, H Sanusi. Regional Engineering Postgraduate Conference


(EPC) 2011.UKM, 4 5 October 2011.
THANK YOU