PRESENTATION

COMPUTER DESIGN AND ORGANIZATION

Group Assignment I
Presented by Group-4 members
1.Belihu ayele079/05
2.G/medhin hagush o8o/05
3.Shiferaw geresu 090/05
 Group Assignment -I
Design the data path architecture for the following
micro operation of one machine cycle.
T1:A-Bus PC (CPU)
T2: C-Bus RD(CPU)
PC PC+1
T3: D-Bus MEM.DATA
T4: I-Reg D-Bus
Assume :ALU has 16-arthmetic and
16 logical operation
Components: ALU
Mux
D-reg1
D-reg2
I-reg
A-reg
DATAPATH
INTRODUCTION
A datapath is a collection of functional units, such as
arithmetic logic units or multipliers, that perform data
processing operations.
The datapath is capable of performing certain operations on
data items. The flow of data between registers &
arithmetic operations are performed in the data
path.The control section is basically the control unit, which
issues control signals to the datapath. Internal to the CPU,
data move from one register to another and between ALU
and registers. Internal data movements are performed via
local buses, which may carry data, instructions, and
addresses. Externally, data move from registers to memory
andI/O devices, often by means of a system bus. Dedicated
data paths may also be used between components that
transfer data between themselves more frequently.
A typical CPU has components as:
1. ARTHIMATIC LOGIC UNIT(ALU)
The Arithmetic Logic Unit is responsible for bit operations on
data held in the AC (Accumulator) and MBR (Memory Buffer
Register) and for storing the results
It capable of Arithmetic and logic function units is performs 16
bit arithmetic functions and 16 bit logic functions
Arithmetic (additions ,sub )
Logic (AND, OR, XOR..)
ALU have 5 control unit it performs by these control unit
25 =32 functions...
2.PROGRAMME COUNTER (PC)
PC Connected to the internal address bus, the Program Counter holds the
address in memory of the next program instruction. Notice that it doesn't
Connect directly to the memory, but must go via the the MAR.(Memory Address
Register)
3. INSTRUCTION REGISTER
which is used to hold the instruction that is currently executed.
IR When memory is read, the data first goes to the MBR. If the data is an
Instruction it gets moved to the Instruction Register. The IR has two parts:

3.1. IR (opcode) the most significant bits of the instruction make up the op-
Code. This the real instruction part of the instruction, that tells the cpu
what to do. The instruction in IR (opcode) gets decoded and executed by
the control unit, CU.
3.2 IR (address) The least significant bits of the instruction are actually data.
They get moved to IR (address). As the name suggests they usually form
all or part of an address for later use in the MAR. (Sometimes | actually
in immediate addressing | they are sent to the AC.)
4 .ADRESS REGISTOR
The Memory Address Register is used to store the address to access
Memory.
5. ACUMULATOR
The Accumulator is used to store data that is being worked on by the
ALU, and is the key register in the data section of the CPU. Notice that the
memory can't access the AC directly. The MBR is an intermediary.
6. MULTIPLEXER (MUX)
It has multiple input (by control unit) selects single out put or selected
A multiplexer of 2n inputs has n select lines, which are used to select which input line
to send to the output.
7.THE CONTROL UNIT :-is the entity responsible for fetching the instruction to be
executed from the main memory and decoding and then executing it.
The CPU fetches instructions from memory, reads and writes data from and to memory,
and transfers data from and to input/output devices.
8. DATA REGISTER :-is a region of memory storage within a computer commonly
used as a temporary storage for data to or from a peripheral device or memory.
ONE MACHINE CYCLE
T1 A.BUS PC (CPU)
T2 C.BUS RD (CPU)
PC PC +1
T3 D.BUS M.DATA
T4 I.REGR D.BUS
 DATAPATH ARCHITECTURE
C-bus
CONTROL
INST_REGR ADRESS BUS

DATA
ADRE _REGR M BUS
U
X
1 memory
DATA1_REGR

ALU
DATA2_REGR 0/1
MUX0

PC

0/1 ACCUMULATOR
 T1 A.BUS PC (CPU)
(Address bus) (Program counter)

Cpu (central processing unit) placed the address bus the address
of the next instruction to be fetched . Address is sent to
memory by the address bus
T1 A.BUS PC (CPU) C-bus
CONTROL

IN_REGR

ADRESS BUS

AD _REGR M
U memory
X
1
D1_REGR

ALU
D2_REGR 0/1
MUX0

PC

S4S3S2S1S0

0/1 ACCUMULATOR
T2 C.BUS RD (CPU)
(Control bus) (Read)
PCPC+1

CPU sends read signal(RD) to memory

PCPC+1
The program counter must be incremented and go to the next
memory location
 T2 C.BUS RD (CPU)
C-bus
CONTROL
INST_REGR ADRESS BUS

DATA
ADRE _REGR M BUS
U
X
1 memory
DATA1_REGR

ALU
DATA2_REGR 0/1
MUX0

PC

ACCUMULATOR
 T3 D.BUS M.DATA
(Data Bus) (Memory Data)
data from a memory placed in data bus
The memory responds immediately or if the memory is not ready, a wait state TW: is introduced
until it is ready with the required data) then data from memory is placed on the D-bus via MUX 1
C-bus
CONTROL
INST_REGR
ADRESS BUS
data-bus

ADRE _REGR M
U
X
1
DATA1_REGR memory

ALU
DATA2_REGR 0/1
MUX0

PC
S4S3S2S1S0

0/1
 T4) I.REGR D.BUS

Data is sent to IR through databus

On the data bus be fetched to the instruction register
C-bus
CONTROL
INST_REGR
ADRESS BUS
data-bus

ADRE _REGR M
U
X
memory
DATA1_REGR

ALU
DATA2_REGR 0/1
MUX

PC
S4S3S2S1S0

0/1
 System Architecture

SYSTEM BUS
R
R D
D R
Addr Y Addr DATA
DATA D
Y
ADDRESS CONTROL INSTRUCTIO
PC N
DECODER
I -REG

Addr DATA
DECODER M M R
A U
U D
L X
X CNTRL
U 1
0

0/1 0/1
C4
C3
C2
C1
c0

MEMORY
Control input
DATA
REGISTER1 DATA
REGISTER2
CPU
 I-REGR AD-REGR D1-REGR D2-REGR MUX0 MUX 1
PC ALU
IN OUT IN OUT IN OUT IN OUT IN OUT

Let assume the the ALU conrol input /selector 00101 then the when
we take the instruction at T1
I-REGR AD-REGR D1-REGR D2-REGR MUX0 MUX 1
PC ALU
IN OUT IN OUT IN OUT IN OUT IN OUT

T1: 0 0 1 1 0 0 0 0 0 1 1 1 0 0 1 0 1

Addres MEM
T1 in memory as Decoder T1
microword

Test the information (input) then

what is to be next state and Test Next controller out
generate controlled signal
 Algorithmic State Machine chart

T1 ABUS PC

CBUS RD(CPU)
T2 P PC+1

Here The memory responds immediately or if the memory is not ready, a wait state
TW: is introduced until it is ready with the required data) then data from memory is
placed on the D-bus via MUX 1
1 0
T3 READY?

Tw
DATA BUS MEMORY
DATA 1 0
READY?

T4 IREG DATA BUS

simple execution cycle can be summarized as
follows:
1. The next instruction to be executed, whose
address is obtained from the PC, is fetched from
the memory and stored in the IR.
2. The instruction is decoded.
3. Operands are fetched from the memory and
stored in CPU registers, if needed.
4. The instruction is executed.
5. Results are transferred from CPU registers to the
memory, if needed.
The execution cycle is repeated as long as there are
more instructions to execute.
Reference :Our class lecture
professor S.Raman lecture
www.google .com
End!!!!!!!!!!!!
Thank you