555 Timer

Timer - Introduction
Timer is a highly stable device for generating time delay
or oscillation
SE555/NE555
Package: 8 pin circular style, TO-99 can, 8 pin mini DIP,
14 pin DIP
556 timer is a 14 pin DIP contains two 555 timers
Time delay from micro seconds to hours
Supply : +5V to +18V
Load: drive load up to 200 mA
Applications: Oscillator, pulse generator, ramp and
square wave generator, mono shot multivibrator, burglar
alarm, traffic light control and voltage monitor.
Pin Diagram
Functional diagram
 Description
The voltage divider has three equal 5k resistors. It
divides the input voltage (Vcc) into three equal parts.
The two comparators are op-amps which compare
the voltages at their inputs and saturate depending
upon which is greater.
The flip-flop is a bi-stable device. It generates two
values, a high value equal to Vcc and a low value
equal to 0V.
The transistor is being used as a switch, it connects
pin 7 (discharge) to ground when it is closed
RS Flip Flop
Monostable Multivibrator
Monostable operation
 Steps
Initially 555 is reset, Q=0, Qb=1.Hence output(Q)=0
Pin no.6 is almost at GND since Qb turns ON Transistor Q1 and drives
it to saturation
When a negative trigger is applied at 2,S becomes logic 1.FF is set,
i.e. output(pin no3) goes high.
Now, Qb being 0 turns off Transistor Q1
So, capacitor C , being connected to Vcc through R starts charging
towards Vcc
The moment capacitor voltage > 2Vcc/3,R becomes 1,resetting the
FF. Hence output(Q) becomes 0.
Qb becomes 1 which quickly turns ON the transistor and discharges
the capacitor voltage
Circuit stays in 0 until a trigger comes again
 Monostable operation

The pulse width of time t, which is the time it takes to charge C to 2/3 of the
supply voltage, is given by
ASTABLE OPERATION
 Steps
When Vcc is applied the capacitor starts charging.
Capacitor C will charge towards Vcc through Ra and Rb
When C voltage crosses Vcc/3,S=1.This makes Q=1 and Qb=0.The
transistor is cut off and the capacitor continues to charge .
when C voltage crosses 2Vcc/3,output of upper comparator
becomes 1,resetting the flip flop.
Thus output(Q) becomes 0,Qbar =1 which turns ON Q1
Now, C has a path to discharge through Rb (through Q1)(current
from Vcc also flows through Ra and Q1 to GND)
C voltage decreases exponentially till it becomes just below Vcc/3.At
this instant. Lower comparator is triggered and FF is set(S=1)
Hence output(Q) becomes high again. Qbar becomes 0 which turns
OFF Q1.Hence Capacitor cannot discharge, but starts charging
towards Vcc through Ra and Rb. Cycle repeats
 Astable -Time period

Charging Interval: TH RA RB C ln2

Discharging Interval: TL RB C ln2
Period of Oscillation: TH TL RA 2RB C ln2
1 1
Frequency of Oscillation:
T R A 2RB C ln2
TH R A RB
Duty Cycle: d = 100% 100%
T R A 2RB