Complementary CMOS Inverter DC Characteristics

Complementary CMOS inverter
DC characteristics
Ms.Saritha B M,Lecturer,PESITM,SMG 1
Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will

3) If the supply voltage of a chip increases, the maximum transistor current will
4) If the width of a transistor increases, its gate capacitance will

5) If the length of a transistor increases, its gate capacitance will

6) If the supply voltage of a chip increases, the gate capacitance of each transistor will
1) If the width of a transistor increases, the current will
2) If the length of a transistor increases, the current will

3) If the supply voltage of a chip increases, the maximum transistor

current will
4) If the width of a transistor increases, its gate capacitance will

5) If the length of a transistor increases, its gate capacitance will

6) If the supply voltage of a chip increases, the gate capacitance of

each transistor will
nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vdsn < Vgsn Vtn Vdsn > Vgsn Vtn
VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn
Vtpn > 0
nMOS Operation
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn Vtn Vdsn > Vgsn Vtn
Vout < Vin - Vtn Vout > Vin - Vtn
pMOS Operation
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vdsp > Vgsp Vtp Vdsp < Vgsp Vtp
Vgsp = Vin - VDD

Vdsp = Vout - VDD VDD
Vtp < 0 Idsp

Vin Vout
Idsn
pMOS Operation
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp Vtp Vdsp < Vgsp Vtp
Vout > Vin - Vtp Vout < Vin - Vtp
I-V Characteristics
Current vs. Vout, Vin
Vin0 Vin5
Vin1 Vin4
Idsn, |Idsp|
Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
Load Line Analysis
For a given Vin:
Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal in
Vin0 Vin5
Vin1 Vin4
Idsn, |Idsp|
Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
Load Line Analysis
Vin = 0
Vin0
Idsn, |Idsp|
Vin0
VDD
Vout
Load Line Analysis
Vin = 0.2VDD
Vin1
Idsn, |Idsp|
Vin1
VDD
Vout
Load Line Analysis
Vin = 0.4VDD
Idsn, |Idsp|
Vin2
Vin2
VDD
Vout
Load Line Analysis
Vin =0.6VDD
Idsn, |Idsp|
Vin3
Vin3
VDD
Vout
Load Line Analysis
Vin = 0.8VDD
Vin4
Idsn, |Idsp|
Vin4
VDD
Vout
Load Line Analysis
Vin = VDD
Vin0 Vin5
Vin1
Idsn, |Idsp|
Vin2
Vin3
Vin4
VDD
Vout
Load Line Summary
Vin0 Vin5
Vin1 Vin4
Idsn, |Idsp|
Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
DC Transfer Curve
Transcribe points onto Vin vs. Vout plot
Vin0 Vin5
Vin1 Vin4
VDD
Vin2 Vin3
A B
Vin3 Vin2
Vin4 Vin1
VDD
Vout Vout
C
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin
Operating Regions and supply current
Region nMOS pMOS VDD
A Cutoff Linear
A B
B Saturation Linear
C Saturation Saturation Vout
D Linear Saturation C
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin
Supply Current IDD VS Vin

Region Condition nMOS pMOS Output
A 0 < Vin < Vtn Cutoff Linear Vout= Vdd
B Vtn < Vin < Vdd/2 Saturation Linear
C Vin = Vdd/2 Saturation Saturation
D Vdd/2 < Vin < Linear Saturation

Vdd- |Vtp|
E Vin > Vdd - |Vtp| Linear Cutoff Vout = Vss
PMOS Load Lines
VDD
G S
IDn
D
V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp Vin Vout
D
G CL
V out
S
IDp IDn IDn

Vin=0 Vin=0
Vin=3 Vin=3
V DSp V DSp Vout

VGSp=-2
VGSp=-5
Vin = V DD+VGSp Vout = V DD+VDSp
IDn = - IDp
CMOS Inverter Load Lines
PMOS X 10-4 NMOS

2.5
Vin = 0V Vin = 2.5V
2
1.5
Vin = 0.5V Vin = 2.0V
1
Vin = 1.0V
Vin = 1.5V Vin = 1V Vin = 1.5V
Vin = 2V Vin = 0.5V
0.5
Vin = 1.5V Vin = 1.0V
Vin = 2.0V Vin = 0.5V
0
V = 2.5V
in
0 0.5 1 1.5 2 2.5 Vin = 0V
Vout (V)
0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
CMOS Inverter VTC
NMOS off
2.5
PMOS linear
NMOS sat
PMOS linear
2
1.5 NMOS sat
Vout (V)
PMOS sat
1
0.5 NMOS linear
PMOS sat NMOS linear
PMOS off
0
0 0.5 1 Vin
1.5
(V)
2 2.5
Complementary CMOS inverter
with capacitor load CL
Beta Ratio (bn / bp )
If bp / bn 1, switching point will move from
VDD/2
Called skewed gate.
In order to explore the variations in transfer

characteristic as a function of bn / bp ,
the transfer curve for several values of beta
ratio are plotted in fig (1).
Contd
If we want to change beta ratio, need to change the channel
dimensions , i.e., channel length L , channel width W shown
in fig(3).
As in Fig (1), as the beta ratio decreased, the transition
region shifts from left to right .
However, the output voltage transition remains sharp.
For Cmos inverter a ratio of
bn / bp = 1
The inverter transfer curve is also plotted for Wn / Wp.
It shows relative shift to the left.
Beta ratio bp / bn
VDD
bp
= 10
bn
Vout 2
1
0.5
bp
= 0.1
Fig (2)
bn
0
VDD
V in
Temperature effect
Tempr also has an effect on the transfer
characteristic on inverter.
As the tempr of an MOS device increased, the
effective carrier mobility decreases.
This results in a decrease in which relates to
temperature T is
T (-1.5)
therefore ,
Ids T (-1.5)
Noise margin or Noise Immunity
Parameter related to input-output voltage
characteristics.
Determines allowable noise voltage on the input
of a gate so that output will not be affected.
or
maximum noise voltage on the input of a gate
that allows the output to be remain stable.
Contd
Noise margin is specified in terms of two
parameters.
1. Low noise margin NML
2. High noise margin NMH
Low Noise margin difference in magnitude
between the maximum low output voltage of the
driving gate and the maximum low input voltage
recognized by the receiving gate.
i.e, NML = | VILmax VOLmax |
Contd
High Noise margin difference in magnitude
between the minimum high output voltage of the
driving gate and the minimum high input voltage
recognized by the gate.
i.e, NMH = | VOHmin VIHmin |
Where,
VIHmin - minimum high input voltage
VILmax - maximum low input voltage
VOHmin - minimum high output voltage
VOLmax - minimum low output voltage
Noise Margin Definitions
Contd
To maximize noise margins, select logic levels at unity
gain points of DC characteristics.
Contd
CMOS inverter noise margins
Contd
CMOS inverter noise margins
1) Calculate VM
2) Calculate gain AV
3) Calculate NML and NMH
Contd
Calculate gain AV
Contd
CMOS inverter as an amplifier
It is an analog amplifier under saturating
conditions.
In region C, Cmos inverter used as an inverting
linear amplifier , i.e.,
Vout = - A Vin
A - stage gain
Gain is calculated by using small signal model of
the amplifier.
Pass Transistors
Transistors can be used as switches
g g=0 Input g = 1 Output

s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1
g g=0 Input Output

g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1
Signal Strength
Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0

But degraded or weak 1
pMOS
pull-up
pMOS pass strong 1 network
inputs
But degraded or weak 0 output
Thus NMOS are best for pull-down network nMOS

pull-down
Thus PMOS are best for pull-up network network
Transmission Gate or Complementary switch
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb
g g g
a b a b a b
gb gb gb
Tristates
Tristate buffer produces Z when not enabled
EN
EN A Y
0 0 A Y
0 1
1 0
EN
1 1
A Y
EN
Tristates
Tristate buffer produces Z when not enabled
EN
EN A Y
0 0 Z A Y
0 1 Z
1 0 0
EN
1 1 1
A Y
EN
Nonrestoring Tristate
Transmission gate acts as tristate buffer
Only two transistors
But nonrestoring
Noise on A is passed on to Y
EN
A Y
EN
Tristate Inverter
Tristate inverter produces restored output
By cascading transmission gate with an
inverter the tristate inverter can be constructed.
A
EN
Y
EN
Tristate Inverter
Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
A A
A
EN
Y Y Y
EN
EN = 0 EN = 1
Y = 'Z' Y=A

Complementary CMOS Inverter DC Characteristics

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Complementary CMOS Inverter DC Characteristics

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Complementary CMOS inverter

2) If the length of a transistor increases, the current will

4) If the width of a transistor increases, its gate capacitance will

5) If the length of a transistor increases, its gate capacitance will

2) If the length of a transistor increases, the current will

3) If the supply voltage of a chip increases, the maximum transistor

4) If the width of a transistor increases, its gate capacitance will

5) If the length of a transistor increases, its gate capacitance will

6) If the supply voltage of a chip increases, the gate capacitance of

Vdsn < Vgsn Vtn Vdsn > Vgsn Vtn

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vin < Vtn Vin > Vtn Vin > Vtn

Vdsn < Vgsn Vtn Vdsn > Vgsn Vtn

Vout < Vin - Vtn Vout > Vin - Vtn

Vdsp > Vgsp Vtp Vdsp < Vgsp Vtp

Vgsp = Vin - VDD

Vtp < 0 Idsp

Vdsp > Vgsp Vtp Vdsp < Vgsp Vtp

Vout > Vin - Vtp Vout < Vin - Vtp

Supply Current IDD VS Vin

A 0 < Vin < Vtn Cutoff Linear Vout= Vdd

B Vtn < Vin < Vdd/2 Saturation Linear

C Vin = Vdd/2 Saturation Saturation

D Vdd/2 < Vin < Linear Saturation

E Vin > Vdd - |Vtp| Linear Cutoff Vout = Vss

IDp IDn IDn

V DSp V DSp Vout

PMOS X 10-4 NMOS

In order to explore the variations in transfer

g g=0 Input g = 1 Output

g g=0 Input Output

VDD and GND rails are strongest 1 and 0

nMOS pass strong 0

Thus NMOS are best for pull-down network nMOS

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