MULTILEVEL INVERTERS

MULTILEVEL
INVERTER
Advanced Power Electronics
B. E. IV (Electrical)
Introduction
In recent years, industry has begun to demand higher power

equipment, which now reaches the megawatt level.
Controlled ac drives in the megawatt range are usually connected
to the mediumvoltage network. It is hard to connect a single
power semiconductor switch directly to medium voltage grids
(2.3, 3.3, 4.16, or 6.9 kV).
The voltage source inverters produce an output voltage with levels
either 0 or Vdc, they are known as twolevel inverter. To obtain a
quality output voltage or a current waveform with a minimum
amount of ripple content, they require high switching frequency
along with various PWM strategies.
Introduction
In high power and high voltage applications, these two-level

inverters have some limitations in operating at high frequency
mainly due to switching losses and constraints of device ratings.
For these reasons, a new family of multilevel inverters has
emerged as the solution for working with higher voltage levels.
Multilevel inverters include an array of power semiconductors and
capacitor voltage sources, the output of which generate voltages
with stepped waveforms.
Increasing the number of voltage levels in the inverter output
without requiring higher ratings of individual devices can increase
the power rating.
Introduction
However, with the increased number of levels, the number of

allowable switching states in the inverters also rapidly increases.
This situation places significant computational challenges in front
of the PWM modulator, which is typically implemented in
software and operating in real time and for high switching speed.
Multilevel Concept
one phase leg of two level and three level inverter and pole voltage vo
Multilevel Concept
Let us consider a 3phase inverter system as shown in fig. with a dc

voltage Vdc. Series connected capacitors constitute the energy tank
for the inverter, providing such nodes to which the multilevel
inverter can be connected. Each capacitor has same voltage, which
is given by,
Vdc
Em
m 1
Where m=numbers of level.

The term level is referred to numbers of nodes to which inverter can
be accessible. An mlevel inverter needs (m1) capacitors.
Multilevel Concept
Multilevel Concept
Output phase voltage can be defined as voltages across output

terminals of the inverter and the ground point denoted by O as
shown in fig.
Multilevel Concept
Fig shows the schematic of a pole in a multilevel inverter where v 0
indicates an output phase voltage that can assume any voltage

level depending on the selection of node (dc) voltage V1, V2, etc.
Thus, a pole in multilevel inverter can be regarded as a single-
pole, multiple-throw switch. By connecting the switch to one node
at a time, one can obtain the desired output.
Output voltage of a five-level inverter has been shown in the fig.
Types of Multilevel Inverters
The general structure of the multilevel converter is to synthesize a

near sinusoidal voltage from several levels of dc voltages,
typically obtained from capacitor voltage sources.
As the no. of levels increases, the synthesized output waveform
has more steps, which will produce a staircase wave that
approaches a desired waveform.
Also, as more steps are added to the waveform, the harmonic
distortion of the output wave decreases, approaching to zero as the
number of levels increases.
As the no. of level increases, the voltage the can be spanned by
summing multiple voltage levels also increases.
Types of Multilevel Inverters
Generally, the capacitor terminal voltages E1, E2, all have same
value Em.
Thus, the peak voltage is va0(peak) = (m1) Em = Vdc.
To generate an output voltage with both +ve and ve values, the
circuit topology has another switch to produce ve part vob so that
vab = va0 vb0 = va0+ v0b.
The multilevel inverters can be classified into three types:

I. Diodeclamped
II. Flyingcapacitors
III. Cascade
Diode Clamped Multilevel Inverters
A diode clamped multilevel inverter is based on concept of using

diodes to limit voltage stresses of devices.
It consists of series connected capacitors that divide DC bus
voltage in to set of capacitor voltages.
For mlevel inverter, it comprises (m1) capacitors on the DC bus
and gives Vdc voltage across each capacitor.
( m 1)
Fig. shows typical power circuit of 3ph, 3level Inverter.

A one phase leg of threelevel diodeclamped

inverter is shown in Fig.
In this circuit, the dcbus voltage is split into
three levels by two seriesconnected bulk
capacitors, C1 and C2. The middle point of the
two capacitors n can be defined as the neutral
point.
Switches S11 and S14 function as main switches
(like a two level inverter) while S 12 and S13
function as auxiliary switches which help
clamp the output potential to the neutral point
with the help of clamping diodes D 10 and D10.
The output pole voltage has three states: +Vdc/2, 0, and Vdc/2.
For voltage level +Vdc/2, switches S11 and S12 need to be turned on;
for Vdc/2, switches S13 and S14 need to be turned on; and for the 0
level, S12 and S13 need to be turned on as shown in fig.
The key components that distinguish this circuit from a conventional
twolevel inverter are clamping diodes D 10 and D10. These two diodes
clamp the switch voltage to half the level of the dcbus voltage.
When both S11 and S12 turn on, the voltage across a and 0 is Vdc, i.e.,
va0 = Vdc.
In this case, D10 balances out the voltage sharing between S 13 and S14
with S13 blocking the voltage across C 1; and S14 blocking the voltage
across C2.
Notice that output voltage van is ac, and va0 is dc.
If the output is observed between a and 0, then the circuit becomes a
dc/dc converter, which has three output voltage levels:V dc, +Vdc/2 and
0.
Fig. shows a five-level diode-

clamped converter in which the dc
bus consists of four capacitors, C1,
C2, C3 and C4.
For dcbus voltage Vdc, the voltage

across each capacitor is Vdc/4, and
each device voltage stress will be
limited to one capacitor voltage
level Vdc/4 through clamping
diodes.
To explain how the staircase voltage is synthesized, the neutral

point n is considered as the output phase voltage reference point.
There are five switch combinations to synthesize five level voltages
across a and n.
1) For voltage level Van = Vdc/2, turn on all upper switches S1S4.
2) For voltage level Van = Vdc/4, turn on three upper switches S2S4
and one lower switch S1.
3) For voltage level Van = 0, turn on two upper switches S3 and S4
and two lower switches S1 and S2.
4) For voltage level Van = Vdc/4, turn on one upper switch S4 and
three lower switches S1S3.
5) For voltage level Van = Vdc/2, turn on all lower switches S1
S4.
Although each active switching device is only required to block a

voltage level of Vdc/(m1), the clamping diodes must have
different voltage ratings for reverse voltage blocking.
Using D1 of Fig. as an example, when lower devices S2S4 are
turned on, D1 needs to block three capacitor voltages, or 3Vdc/4.
Similarly, D2 and D2 need to block 2Vdc/4, and D3 need to block
3Vdc/4.
Diode Clamped Multilevel Inverters From Rashid
A diode clamed multilevel(m-level) inverter typically consists of

(m1) capacitors on the dc bus and produces m levels on the ph
voltage.
Fig(a) shows one leg and fig.(b) shows a full-bridge five-level
diode-clamed converter.
Four capacitors: C1 C4.
For a dc bus voltage Vdc, the voltage across each cap is Vdc/4, and
each device voltage stress is limited to one capacitor voltage level
Vdc/4 through clamping diodes. An m-level inverter leg requires
(m1) capacitors, 2(m1) switching devices and (m1)(m2)
clamping diodes.
Principle of Operation
To produce a staircase output voltage, only one leg of five-level inverter is

considered. The dc rail 0 is the reference point of the output phase voltage.
Steps to synthesize the five-level voltages are:
1) For an output voltage level Vao = Vdc, turn on all upper-half
switches Sa1 through Sa4.
2) For an output voltage level Vao = 3Vdc/4, turn on three upper
switches Sa2 through Sa4 and one lower switch Sa1.
3) For an output voltage level Vao = Vdc/2, turn on two upper switches
Sa3 through Sa4 and two lower switches Sa1 and Sa2.
4) For an output voltage level Vao = Vdc/4, turn on one upper switch Sa4
and three lower switches Sa1 through Sa3.
5) For an output voltage level Vao = 0, turn on all lower half switches
Sa1 through Sa4.
State condition 1 means s/w is ON and state 0 means s/w is OFF.

Each s/w is turned on only once per cycle and there are four
complementary switch pairs in each ph.
These pairs for one leg of the inverter are: (Sa1,Sa1), (Sa2,Sa2),
(Sa3,Sa3) and (Sa4,Sa4).
Thus, if one of the complimentary switch pair is turned on, the
other of the same pair must be off.
Four switches are turned on at a time.
Fig shows the phase voltage waveform of the five-level
inverter. The line voltage consists of the +ve phase-leg voltage
of terminal a and the ve phase-leg voltage of terminal b.
Each phase-leg voltage tracks one-half of the sinusoidal wave.

Resulting line voltage is a nine-level staircase wave.
This implies that an m-level converter has an m-level output
phase-leg voltage and a (2m1)-level output line voltage.
Features of Diode Clamped Multilevel Inverters
From Rashid
1. High Voltage rating for blocking diodes:
Although each switching device is only required to block a
voltage level of Vdc/ (m1), the clamping diodes need to have
different voltage blocking ratings.
For Ex. When all lower devices Sa1 through Sa4 are turned on,
diode Da1 needs to block three capacitor voltages, or 3Vdc/4.
Similarly, diodes Da2 and Da2 need to block 2Vdc/4, and Da3
needs to block Vdc/4.
Even though each main switch is supposed to block the
nominal blocking voltage, the blocking voltage of each
clamping diode is dependent on its position in the structure.
From Rashid
If the blocking voltage rating of each diode is same as that of
the switching device, the no. of diodes required for each
phase is ND = (m1) (m2). This number represents a
quadratic increase in m. Thus, for m= 5, ND = (51)(52) = 12.
When m is sufficiently high, the number of diodes makes the
system impractical to implement, which limits the number of
levels.
From Rashid
2. Unequal switching device rating:
We can notice from table that switch Sa1 conducts only during
Vao = Vdc, whereas switch Sa4 conducts over entire cycle
except during the interval Vao = 0.
Such an unequal conduction duty requires different current
ratings for the switching devices.
Therefore, if the inverter design uses the average duty cycle
to find the device ratings, the outer switches may be
oversized, and the inner switches may be undersized.
From Rashid
3. Capacitor voltage unbalance :
Because the voltage levels at the capacitor terminals are
different, the current supplied be the capacitors are also
different.
When operating at unity power factor, the charging and
discharging time for each capacitor is different.
Such a capacitor charging profiles repeats every half cycle, and
the result is unbalanced capacitor voltage between different
levels.
This problem can be resolved by replacing capacitors by a
controlled constant dc voltage source, PWM regulators, or
batteries.
Advantages
When the number of level is high enough, the harmonic
content is low enough to avoid the need for filters.
Inverter efficiency is high because all devices are switched at
the fundamental freq.
The control method is simple.
Disadvantages
Excessive clamping diodes are required when no. of levels is
high.
It is difficult to control the real power flow of the individual
converter in multiconverter systems.
Improved Diode Clamped Inverter
The problem of multiple

blocking voltages of the
clamping diodes can be
addressed by connecting
number of diodes in series.
However, due to mismatch
of the diode characteristics,
the voltage sharing is not
equal.
Modified diode-clamped inverter with distributed
clamping diodes
Five level inverter
Total 8 switches: S1, S2, S3, S4,
S1, S2, S3 and S4
12 diodes of equal voltage
rating
Total (m1) = 4 capacitors
2(m1) = 8 capacitors
(m1) (m2) = 12 clamping
diodes
clamping diodes Principle of operation
The modified diode-clamped inverter can be decompsed into
two-level switching cells.
For an m-level inverter, there are (m1) switching cells. For 5-
level there are 4 cells.
Cell1: S2, S3, and S4 are always on whereas S1 and S1 are
switched alternatively to produce an output voltage Vdc/2 and
Vdc/4, respectively.
switched alternatively to produce an output voltage Vdc/4 and 0,
respectively.
switched alternatively to produce an output voltage 0 and V dc/2 ,
respectively.
Cell4: S1, S2 and S3 are always on whereas S 4 and S4 are

switched alternatively to produce an output voltage V dc/4 and
Vdc/2, respectively.
Each switching cell works as a normal two-level inverter, except
that each forward or freewheeling path in the cell involves (m1) =
4 devices instead of only one.
For an ex., for cell2 the forward path of up-arm D 1, S2, S3,
and S4, whereas freewheeling path of up-arm S1, D12, D8, and
D2, connecting inverter o/p to V dc/4.
The forward path of down-arm S1, S2, D10, and D4, whereas
freewheeling path of down-arm D3, D7, S3 and S4,
connecting inverter o/p to 0.
Flying-Capacitors Multilevel Inverters
Fig. illustrates the fundamental building block of
a phase-leg capacitor-clamped inverter. The
circuit has been called the flying capacitor
inverter.
The inverter in Fig. 3(a) provides a three-level
output across a and n, i.e., Van = Vdc/2, 0, or
Vdc/2.
For voltage level +Vdc/2, switches S1 and S2 need
to be turned on.
For voltage level Vdc/2, switches S1 and S2 need
to be turned on.
For 0 voltage level, either pair (S 1,S1) or (S2,S2)
needs to be turned on.
The voltage of the five-level phase-leg a output with respect to
the neutral point n, Van, can be synthesized by the following
switch combinations.
1. For an output voltage level Van = Vdc/2, turn on all upper
switches S1 S4.
2. For voltage level Van = Vdc/4, there are three combinations:

a) S1, S2, S3, S1 (Van = Vdc/2 of upper C4s Vdc/4 of C1);
b) S2, S3, S4, S4 (Van = 3Vdc/4 of C3s Vdc/2 of lower C4 s); and
c) S1, S3, S4, S3 (Van = Vdc/2 of upper C4s 3Vdc/4 of Cs s + Vdc/2 of C2
s )
3. For voltage level Van = 0 , there are six combinations:

a) S1, S2, S1, S2 (Van = Vdc/2 of upper C4s Vdc/2 of C2s);
b) S3, S4, S3, S4 (Van = Vdc/2 of C2s Vdc/2 of lower C4s);
c) S1, S3, S1, S3 (Van = Vdc/2 of upper C4s, 3Vdc/4 of C3s + Vdc/2 of C2
s Vdc/4 of C1 );
d) S1, S4, S2, S3 (Van = Vdc/2 of upper C4s, 3Vdc/4 of C3s + Vdc/4 of C1
);
e) S2, S4, S2, S4 (Van = 3Vdc/4 of C3s Vdc/2 of C2 s +Vdc/4 of C1
Vdc/2 of lower C4s ); and
f) S2, S3, S1, S4 (Van = 3Vdc/4 of C3s Vdc/4 of C1 Vdc/2 of lower C4s
)
4. For voltage level Van = Vdc/4, there are three combinations:
a) S1, S1, S2 , S4 (Van = Vdc/2 of upper C4s 3Vdc/4 of C3s);
b) S4, S2, S3, S4(Van = Vdc/4 of C1 Vdc/2 of lower C4s); and
c) S3, S1, S3, S4 (Van = Vdc/2 of C2s, Vdc/4 of C1 Vdc/2 of lower C4s)
5. For voltage level Van = Vdc/2, turn on all lower switches S 1

S4.
Similar to diode clamping, the capacitor clamping requires a large

number of bulk capacitors to clamp the voltage.
Provided that the voltage rating of each capacitor used is the same as
that of the main power switch, an m-level converter will require a
total of (m1)(m2)/2 clamping capacitors per phase leg in addition
to (m1) main dc-bus capacitors.
Flying-Capacitors Multilevel Inverters From Rashid
The voltage level for the flying-capacitors converter is similar

to that of the diode-clamped converter. i.e. the ph voltage Vao of
an m-level converter has m levels and the line voltage Vab has
(2m1) levels.
Assuming each cap has same voltage rating as the switching
device, the dc bus need (m1) capacitors for an m-level
converter. m
The number of capacitors reqd for each ph is N = (m j ).

C
j 1
Thus, for m=5, NC =10.

To produce a staircase o/p voltage, one leg of the five level

inverter is considered. The dc rail 0 is the ref pt. of the o/p h
voltage.
The steps to synthesize the five level voltage are:
1. For an output voltage level Vao = Vdc, turn on all upper
switches Sa1 Sa4.
2. For voltage level Vao = 3Vdc/4, there are four combinations:

a) Vao = Vdc Vdc/4 (Devices: Sa1, Sa2, Sa3, and Sa4)
b) Vao = 3Vdc/4 (Devices: Sa2, Sa3, Sa4 and Sa1)
c) Vao = Vdc 3Vdc/4 + Vdc/2 (Devices: Sa1, Sa3, Sa4, and Sa2)
d) Vao = Vdc Vdc/2 + Vdc/4 (Devices: Sa1, Sa2, Sa4, and Sa3)
3. For voltage level Vao = Vdc/2, there are six combinations:

a) Vao = Vdc Vdc/4 (Devices: Sa1, Sa2, Sa3, and Sa4)
b) Vao = Vdc/2 (Devices: Sa3, Sa4, Sa1 and Sa2)
c) Vao = Vdc 3Vdc/4 + Vdc/2 Vdc/4 (Devices: Sa1, Sa3, Sa2 and
Sa4)
d) Vao = Vdc 3Vdc/4 + Vdc/4 (Devices: Sa1, Sa4, Sa2 and Sa3)
e) Vao = 3Vdc/4 Vdc/2 + Vdc/4 (Devices: Sa2, Sa4, Sa1 and Sa3)
f) Vao = 3Vdc/4 Vdc/4 (Devices: Sa2, Sa3, Sa1 and Sa4)
4. For voltage level Vao = Vdc/4, there are four combinations:

a) Vao = Vdc 3Vdc/4 (Devices: Sa1, Sa2, Sa3, and Sa4)
b) Vao = Vdc/4 (Devices: Sa4, Sa1, Sa2, and Sa3)
c) Vao = Vdc/2 Vdc/4 (Devices: Sa3, Sa1, Sa2, and Sa4)
d) Vao = 3Vdc/4 Vdc/2 (Devices: Sa2, Sa1, Sa3, and Sa4)
5. For an output voltage level Vao = 0, turn on all lower

switches Sa1 Sa4.
Features of Flying-Capacitors Multilevel Inverters
From Rashid
1. Large number of capacitors:

The inverter requires a large number of storage capacitors.
Assuming that the voltage rating of each capacitor is same as that
of switching device, an m-level converter requires total of (m
1)(m2)/2 auxiliary capacitors per ph leg in addition to (m1)
main dc bus capacitors.
An m-level diode-clamped inverter requires only (m1) capacitors

of the same voltage rating. Thus, for m=5, NC = (43)/2 = 10
compared with NC = 4 for diode-clamped type.
Features of Flying-Capacitors Multilevel Inverters
From Rashid
2. Balancing capacitor voltages:

Unlike the diode-clamped inverter, the FCMLI has redundancy at its
inner voltage levels.
The availability of voltage redundancies allows controlling the

individual capacitor voltages. In producing the same o/p voltages, the
inverter can involve different combinations of capacitors allowing
preferential charging of discharging of individual capacitors.
This flexibility makes it easier to manipulate the capacitor voltages

and keep them at their proper values.
It is possible to employ two or more switch combinations for middle

voltage levels ( i.e., 3Vdc/4, Vdc/2, and Vdc/4) in one or several output
cycle to balance charging and discharging of the capacitors.
Advantages of Flying-Capacitors Multilevel Inverters
From Rashid
Large amounts of storage capacitors can provide capabilities

during power outages.
These inverters provide switch combination redundancy for
balancing different voltage levels.
Like the diode-clamped inverter with more levels, the harmonic
content is low enough to avoid the need for filters.
Both real and reactive power flow can be controlled.
Disadvantages of Flying-Capacitors Multilevel
Inverters From Rashid
An excessive number of storage capacitors is required when the

number of levels is high. High-level inverters are more difficult
to package with the bulky power capacitors and are more
expensive too.
The inverter control can be very complicated, and the switching
freq and switching losses are high for real power transmission.
Cascaded Multilevel Inverters
A cascade multilevel inverter consists of a series of H-bridge
inverter units.
The general function of this multilevel inverter is to synthesize a
desired voltage from several separate dc sources (SDCSs).
Basically, a full-bridge inverter is known as an H-bridge cell,
which is illustrated in fig below.
Vdc B
The inverter circuit consists of four main switches and four
freewheeling diodes.
According to four-switch combination, three output voltage
levels, +Vdc, Vdc and 0, can be synthesized for the voltage
across A and B.
During inverter operation, switches S1 and S4 are closed at the
same time to provide VAB a positive value and switches S2 and
S3 are turned on to provide VAB a negative value.
In case of zero level, there are two possible switching patterns
to synthesize zero level, for example, (1) S1 and S2 on, S3 and S4
off; and (2) S1 and S2 off and S3 and S4 on.
To synthesize a multilevel waveform, the ac output of each of
the different level H-bridge cells is connected in series.
The synthesized voltage waveform is, therefore, the sum of the
inverter outputs.
The number of output phase voltage levels in a cascaded
inverter is defined by
m = 2s +1
where s = the number of dc sources in one phase leg.
A simple gate signal, repeated zero-level patterns, is shown in
Fig below.
All zero levels are generated by turning on S1 and S2. Blanking
time or Dead time must be considered to avoid shoot
through fault.
Vdc
Level 1 S/W ON
Vdc
Level 0 S/W OFF
Repeated zero level switching pattern

S1 and S2 are turned on longer than S3 and S4. As a result, S1 and
S2 consume more power and get higher temperature than the
other two switches.
To avoid such a problem, a different switching pattern for zero
level is applied.
In the first zero stage, S1 and S2 are turned on; then, in the
second zero stage, S3 and S4 are turned on instead of S1 and S2.
By applying this method, turn-on time for each switch turns out
to be equal, a shown in Fig.
Vdc
Vdc
Swapped zero level switching pattern

Fig shows the synthesized phase voltage waveforms of a five-
level cascaded inverter with four SDCSs.
Features of Cascaded Multilevel Inverters
For real power conversion, the cascaded inverters need separate

dc sources.
Connecting dc sources between two converters in a back to back
fashion is not possible because a short circuit can be introduced
when two back to back converters are not switching
synchronously.
Advantages of Cascaded Multilevel Inverters
Compared with diode clamped and flying capacitors inverters, it

requires the less no. of components to achieve the same no. of
voltage levels.
Optimized circuit layout and packaging are possible because
each level has same structure and there are no extra clamping
diodes or voltage balancing capacitors.
Soft switching techniques can be used to reduce switching
losses and device stresses.
Disadvantage of Cascaded Multilevel Inverters
It needs separate DC sources for real power applications,

thereby limiting its applications.
Applications of Multilevel Inverters
Voltage source inverters are used in high-power applications

such as in utility systems for controlled sources of reactive
power.
An inverter can produce a controlled reactive current and
operates as a static volt-ampere reactive (VAR)-compensator
(STATCOM).
These inverters can reduce the physical size of the compensator
and improve its performance during power system
contingencies.
The use of high voltage inverter make possible direct
connection to the high-voltage distribution system, eliminating
the distribution transformer and reducing system cost.
Applications of Multilevel Inverters
The most common applications are

1. reactive power compensation
2. back-to-back intertie
3. variable speed drives.
Reactive Power Compensation
With a purely capacitive load, the inverter operating as a dc-ac
converter can draw reactive current from the ac supply.
Fig shows the circuit diagram of a multilevel converter directly
connected to a power system for reactive power compensation.
The load side is connected to the ac supply and the dc side is
open, not connected to any dc voltage.
For the control of reactive power flow, the inverter gate control
is phase shifted by 180. The dc side capacitors act as the load.
When a multilevel converter draws pure reactive power, the ph
voltage and current are 90 apart, and the capacitor charge and
discharge can be balanced.
Such a converter when serving for reactive power
compensation, is called a static-VAR generator (SVG).
All three multilevel converters can be used in reactive power
compensation.
The relationship of the source voltage vector VS and the converter
voltage vector VC is
VS = VC + jICXS
where IC is the converter current vector, and X S is the reactance of
the inductor LS.
Converter voltage is in phase
with the source voltage with a
leading reactive current (fig a)
and lagging reactive current
(fig b).
Polarity and the magnitude of the reactive current are controlled

by the magnitude of the converter voltage VC.
Back-to-Back Intertie
Fig shows two diode-clamped multilevel converters that are
interconnected with a dc capacitor link.
The left-hand side converter serves as the rectifier for utility
interface, and the right-hand side converter serves as the
inverter to supply ac load.
Each switch remains on once per fundamental cycle.
The voltage across each capacitor remains well balanced, while
maintaining the staircase voltage wave, because the unbalance
capacitor voltages on both sides tend to compensate each other.
Such a dc capacitor link is categorized as the back-to-back
intertie.
The back-to-back intertie that connects two asynchronous
systems can be regarded as (1) a freq changer, (2) a ph shifter, or
(3) a power flow controller.
The power flow between two systems can be controlled
bidirectionally.
Fig shows the phasor diagram for real power transmission from
source end to the load end.
The diagram indicates that the source current can be leading or
lagging the source voltage.
The converter voltage is ph shifted from source voltage with a
power angle, .
If the source voltage is constant, then the current or power flow
can be controlled by the converter voltage.
For =0, the current is either 90 leading or lagging only
reactive power is generated.
Adjustable Speed Drives
The back-to-back intertie can be applied to an adjustable speed
drive (ASD) where the input is the constant freq ac source from
utility supply and the output is the variable freq ac load.
For an ideal system, it requires unity power factor, negligible
harmonics, no electromagnetic interference and high efficiency.
The major differences, when using the same structure for ASDs
and for back-to-back interties, are the control design and size of
the capacitor.
Because the ASD needs to operate at different freqs, the dc-link
capacitors need to be well sized to avoid large voltage swings
under dynamic conditions.
Switching Device Currents
Three level half bridge inverter
V0 and I0 rms load voltage and current
Sinusoidal output current i0 = Im sin(t )
where Im is the peak value of the load current and is the load
impedance angle.
The most inner switches S4 and S1
carry more current than the most
outer switches S1 and S4.
Each input node current can be
expressed as a function of the
switching function SFn as given by
in = SFn i0 for n = 1, 2, ,m
Because the single-pole multiple-throw switch multilevel
inverter is always connected one and only one input node at
every instant, the output load current could be drawn from one
and only one input node. That is,
m
i0 in
n 1
m
RMS value is I 2 0( rms ) I 2 n ( rms )
n
where In(rms) is the rms current of the nth node given by

2
1
SFni
2
I n ( rms ) 0 d (t ) for n = 1, 2, ,m
2 0
For balanced switching with respect to the ground level,
i21(rms) = i25(rms), and i22(rms) = i24(rms)
For given structure, the currents through opposite switches such
as S1,, S4 would have same rms current through S4,, S1.
DC-Link Capacitor Voltage Balancing
The voltage balancing of capacitors acting as an energy tank is

very important.
Fig shows schematic of five-level inverter, stepped o/p voltage
and sinusoidal load current i0 = Im sin(t ).
The ave value of input node current i1 is given by

2 2
1 1
I1( ave)
2 i0 d (t ) 2 I m sin(t )d (t )
2 2
Im
cos cos 2

Similarly, the ave value of input node current i2 is given by

2
1 2
1
I 2( ave)
2 1
i0 d (t )
2 1
I m sin(t )d (t )
Im
cos (cos 1 cos 2 )

By symmetry, I3(ave) =0, I4(ave) = I2(ave), and I5(ave) = I1(ave). Thus,

each capacitor voltage should be regulated so that each
capacitor supplies the ave current per cycle as follow.
Im
I C1( ave) I1( ave) cos cos 2

Im
I C 2( ave) I1( ave) I 2( ave) cos cos 1

Therefore, IC1(ave) < IC2(ave) for 1< 2. This results in the capacitor
charge unbalancing and more charge flows from inner capacitor
C2 (or C3) than that of the outer capacitor C1 (or C4).
Thus, each capacitor voltage should be regulated to supply the

appropriate amount of ave current; otherwise its voltage V C2 (or
VC3) goes to the ground level as time goes.
For n nodes,
Im
I Cn( ave) cos cos n

Now,
cos 2 I C 2( ave)

cos 1 I C1( ave)
This can be generalized for nth and (n 1)th capacitors

cos n I Cn( ave)

cos n 1 I C ( n 1)( ave)
Which means that the capacitor charge unbalancing exists

regardless of the load condition and it depends on the control
strategy such as 1, 2,., n.
Features of Multilevel Inverters
Multilevel inverter can eliminate the need for the step-up
transformer and reduce the harmonics produced by the inverter.
DC bus voltage could be increased beyond the voltage rating of
an individual power device by the use of a voltage clamping
network consisting of diodes.
A multilevel structure with more than three levels can
significantly reduce the harmonic content without implementing
PWM techniques.
Key features of a multilevel structure are:
The output voltage and power increases with number of levels.

Adding a voltage level involves adding a main switching device to
each phase.
The harmonic content decreases as the number of levels increases
and filtering requirements are reduced.
With additional voltage levels, the voltage waveform has more free-
switching angles, which can be preselected for harmonic
elimination.
In the absence of any PWM techniques, the switching losses can be
avoided. Increasing output voltage and power does not require an
increase in rating of individual device.
Static and dynamic voltage sharing among switching devices is
built into the structure through either clamping diodes or
capacitors.
The switching devices do not encounter any voltage-sharing
problems. For this reason, multilevel inverters can easily be
applied for high-power applications such as large motor drives
and utility supplies.

MULTILEVEL INVERTERS

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MULTILEVEL INVERTERS

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MULTILEVEL

In recent years, industry has begun to demand higher power

In high power and high voltage applications, these two-level

However, with the increased number of levels, the number of

Let us consider a 3phase inverter system as shown in fig. with a dc

Where m=numbers of level.

Output phase voltage can be defined as voltages across output

Fig shows the schematic of a pole in a multilevel inverter where v 0

indicates an output phase voltage that can assume any voltage

The general structure of the multilevel converter is to synthesize a

The multilevel inverters can be classified into three types:

A diode clamped multilevel inverter is based on concept of using

Fig. shows typical power circuit of 3ph, 3level Inverter.

A one phase leg of threelevel diodeclamped

Fig. shows a five-level diode-

For dcbus voltage Vdc, the voltage

To explain how the staircase voltage is synthesized, the neutral

Although each active switching device is only required to block a

A diode clamed multilevel(m-level) inverter typically consists of

To produce a staircase output voltage, only one leg of five-level inverter is

State condition 1 means s/w is ON and state 0 means s/w is OFF.

Each phase-leg voltage tracks one-half of the sinusoidal wave.

The problem of multiple

Cell4: S1, S2 and S3 are always on whereas S 4 and S4 are

2. For voltage level Van = Vdc/4, there are three combinations:

3. For voltage level Van = 0 , there are six combinations:

5. For voltage level Van = Vdc/2, turn on all lower switches S 1

Similar to diode clamping, the capacitor clamping requires a large

The voltage level for the flying-capacitors converter is similar

The number of capacitors reqd for each ph is N = (m j ).

Thus, for m=5, NC =10.

To produce a staircase o/p voltage, one leg of the five level

2. For voltage level Vao = 3Vdc/4, there are four combinations:

3. For voltage level Vao = Vdc/2, there are six combinations:

4. For voltage level Vao = Vdc/4, there are four combinations:

5. For an output voltage level Vao = 0, turn on all lower

1. Large number of capacitors:

An m-level diode-clamped inverter requires only (m1) capacitors

2. Balancing capacitor voltages:

The availability of voltage redundancies allows controlling the

This flexibility makes it easier to manipulate the capacitor voltages

It is possible to employ two or more switch combinations for middle

Large amounts of storage capacitors can provide capabilities

An excessive number of storage capacitors is required when the

Repeated zero level switching pattern

Swapped zero level switching pattern

For real power conversion, the cascaded inverters need separate

Compared with diode clamped and flying capacitors inverters, it

It needs separate DC sources for real power applications,

Voltage source inverters are used in high-power applications

The most common applications are

Polarity and the magnitude of the reactive current are controlled

where In(rms) is the rms current of the nth node given by

The voltage balancing of capacitors acting as an energy tank is

The ave value of input node current i1 is given by

Similarly, the ave value of input node current i2 is given by

By symmetry, I3(ave) =0, I4(ave) = I2(ave), and I5(ave) = I1(ave). Thus,

Thus, each capacitor voltage should be regulated to supply the

This can be generalized for nth and (n 1)th capacitors

Which means that the capacitor charge unbalancing exists

The output voltage and power increases with number of levels.

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