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‡ Motivation:
± Reduce number of comparators than a flash ADC
± Flash is feasible only if resolution is small
‡ Idea:
± In a flash ADC, only comparators ³near´ the input
give useful information
± Use a coarse ADC to estimate where the signal is,
then use a fine ADC placed ³around´ the coarse
estimate for better accuracy.
± Also called subranging ADC
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‡ Number of comparators : (2Nc + 2Nf ± 2)

‡ Resolution Nc + Nf bits
‡ ADCs & DAC must be good to (Nc + Nf) bits
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‡ What happens when coarse ADC thresholds have offsets ?

Ɣ Vref exceeds the range of the fine ADC
Ɣ Mitigate this by adding redundant levels (over ranging)
in the fine ADC
Ɣ Able to tolerate large offsets in the coarse ADC

  



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‡ The fine ADC operates on a small input

± Offset requirements for the fine ADC can be
relaxed if the input signal swing was larger
± Amplify the input to the fine ADC
± Typically known as pipelined ADC
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‡ 
 


± ADC ± M bit accurate due to redundancy
± DAC ± N bit accurate
± Gain ± N-M bit accurate

‡ We will calculate all these inaccuracies for 1st stage of a 10b

100Ms/s ADC with 1V reference and 1 bits extracted from each
stage.
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‡ Each stage (except the last) has two task

± Coarse quantization
± Calculated residue


‡ No of comp=2^(1+1)=4
{1 bit redundancy}

‡ Circuit imperfections
± R ladder
± Comparator offset

‡ Offset spec =
(Vfull/No of comp)/2=1/4=250mV
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‡ It does DAC, subtraction and Amplification

‡ Uses the concept of charge sharing.



 
 
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‡ DAC value=Vref*Cs1/(Cs1+Cs2) {Ideally Vref/2}

‡ Mismatch in cap
DAC Value=Vref*[C(1+d)/C(1+d)+C(1-d)]=Vref*(1+d)/2
error=Vref*d/2
‡ Error should be less than LSB of ADC
± Vref*d/2 < 2Vref/2^N
± d < 1/2^(N-2) ~ 1/2^8 [8 bit matching required]
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‡ For a given total resolution of N bits and per

stage resolution of M, the combined gain error in
the inter-stage amplification should be less than
1/2^(N-M)
‡ Error in settling < 1/2^9
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@ In any closed loop feedback system, the gain error is

given by reciprocal of the loop gain

i.e. 1/A*beta < 1/ 2^(N-M)

M is the number of bits resolved in the first stage

Assuming half of the total error is from the finite gain

A > 2*2^9*3 {beta=1/3} = 70dB
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@ If the close loop time constant is tau then the settling

error is e^(-Tsettle/tau)

Assuming half of the total error is from the limited

bandwidth:
Tsettle > 7*tau {7 tau settling is required}

Available settling time is equal to half the sampling period

(Tsamp)

For Tsamp = 1/100M = 10ns

Tsettle=5ns i.e. Tau < 700ps
=> close loop bandwidth = 225MHz
   

‡ High voltage gain speed and swing

requirements.
‡ Some of the amplifier structures used
for
stages are telescopic, two stage, gain
boosting, Folded cascode etc.
‡ Depending on the gain and speed
requirement
a particular architecture is used.




‡ Sampling has to be done exactly at 1/fs interval.

‡ Sampling edges will not be infinitely accurate.
‡ Assuming a sine wave of 50Mhz as input rate of change at zero
crossing is Vw.
‡ If error in sampling has to be less than 1LSB => Vw*jitter =
Vfull/2^N => calculate jitter
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‡ Total input referred noise

± Thermal noise + quantization noise
‡ Thermal Noise:
± Sampling Switches
‡ Used to sample the signal onto the cap. As this happens, noise
from switch is sampled with it onto the cap
‡ Noise Power ~ KT/C
± Opamp
‡ The contribution of opamp is also inversely proportional to C.
‡ Can be alleviated by
± Using large cap
± Oversampling
‡ Both of these remedies increase the power dissipation
 


‡ Total input referred thermal noise is the sum of noise in all stages
‡ How should we distribute the total thermal noise budget among the
stages?
‡ Lets take an example of 1bit/stage 10 bit ADC

‡ Total input referred noise power

 



‡ If we make all caps the same size

± backend stages contribute very little noise
± Wasteful, because Power ~ Gm ~ C
‡ How about scaling caps down by 2^2=4x per stage?
± Same amount of noise from every stage
± All stages contribute significant noise
± Noise from first few stages must be reduced
± Power ~ Gm ~ C goes up!
 



‡ The optimum scaling lies approximately midway between these two

extremes.