Content

Introduction
Basic operation
Circuit diagram
Description
Simulation
Conclusion
Future work
Refrences
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 Abstract
An analog VLSI version of a differential summing amplifier that is based
on the differential difference amplifier. This is a four-input amplifier with
twelve minimal-sized transistors that covers an area that is 120 times less
than previous differential difference amplifier designs which makes it
ideally suited for smart-pixel focal-plane arrays or analog neural networks
that require high-density analog components of minimal size.
The experimental results show that its operation is favorable with the larger
versions for use in open-loop mode, as a voltage follower, or output level-
shifter.

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 Introduction
To improve performance of microsensors and actuators The benefit of on-
chip circuitry is that it creates a self contained system that is smaller,
lighter, and requires less packaging. Since noise is an issue with
microsensors, such as CMOS detectors, the inclusion of processing
circuitry close to the sensor can alleviate this problem. However, by
placing circuitry at the microsensor and micro-actuator, as with focal plane
arrays, the fill factor is reduced. By using small analog components
One circuit that can be used to reduce the affects of mismatch is the
differential difference amplifier This analog building block has four inputs
(two sets of differential inputs) and an output that is a function of the
difference of the difference of the inputs.

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 Basic operation
The standard DDA is implemented using two V-I converters that convert
the differential voltages into currents, which are then subtracted, converted
into a voltage and then amplified . The inputs to the device are Vlp, Vln,
V2p and V2n. One input pair is the formed by M1 and M2 (see Fig. I), the
second is formed by M3 and M4. M5 and M6 are identical transistors that
source the current for the Ml-M2 and M3-M4 pairs. The voltage dbias
controls the amount of current sourced by M5 and M6, which controls the
gain of the device as well as output current levels. Since this is brought off-
chip, the device can be operated with a 5V supply or a 3.3V supply. Thus,
the current that is mirrored by the M7-M8 pair is I4+16, which is defined
as IA, and the current mirrored by M9-M10 is I3+15, which is defined as
IB. IA is mirrored by Mll-M12

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 Cont..
So the output current, Iout, is the difference between IA and IB. The output
current is given by
I = IA- IB = ( I 4 + 16) -( I3+15)
The output current is proportional to the sum of the difference input
voltages

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Circuit diagram

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 Description
A schematic of the A VSLI DSA is shown in Fig. which is derived from the
DDA design presented in However, the original DDA design comprises 16
FETs and the wide-range DDA comprises 32 FETs .The sizes for
transistors M5 and M6 are chosen to obtain bias currents up to a few micro
amps. For transistors MI through M4, the second order effects can be
reduced by making smaller, thus creating a larger linear range. However,
reducing the ratio of W /L to less than 3 results in increased output voltage
offset. So, transistors MI through M4 are significantly larger than the
others in order to improving matching and reduce the output offset, while
minimizing nonlinearity

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Cont

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Simmulation

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Output result

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 Future work
Future work with this component will include the smart optical sensors
with the DSA as part of the sensor. This will demonstrate the ability of the
DSA to reduce nonuniformities that occur in CMOS detectors

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 Refrences
1 E. A. Vinoz, "Analog VLSI Signal Processing: Why, Where, and How?," J.
of VLSI Signal Processing, vol.8, pp. 27-44, 1994.
2 A. H. Titus and T. J. Drabik, "Analog VLSI Implementation of the Help If
Needed Algorithm (HINA)," IEEE Tran. Circuifs and Sysfems II: Analog,
3 S. K. Meudis, S. E. Kemeny, R. C. Gee, B. Pain, C. 0. Staller, Q. Kim, and
E. R. Fossum, "CMOS Active Pixel Image Sensors for Highly Integrated
Imaging Systems, IEEE J. of SSC, vol. 32, pp. 187-196, 1997.
4 M. Cohen and G. Cauwenberghs, "Focal-plane on-line nonuniformity
correction using floating-gate adaptation," presented at 2000 IEEE
Intemational Symposium on Circuits and Systems, Geneva,Switzerland,
2000.

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