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Project Presentation for the Course:

EE 5331- DSP Architectures and Embedded


Systems

Super-CORDIC: An approximation
Based Parallel and Redundant
CORDIC Algorithm

Yugandhara Rao Yadam


(ed16d001)
S.I. Ikram Khan (ee15s082)
Contents

Objective
Conventional CORDIC
Super-CORDIC
A. Rotation Direction and Angle Determination
B. Scaling compensation
Results
Conclusion
Contents

Objective
Conventional CORDIC
Super-CORDIC
A. Rotation Direction and Angle Determination
B. Scaling compensation
Results
Conclusion
Objective: Propose a new CORDIC algorithm in the rotation mode
with reduced
latency
Conventional CORDIC
Trigonometric functions without multiplier
Two modes: Rotation and Vectoring modes
Conventional CORDIC: Circular co-ordinate system
Unified CORDIC: Hyperbolic and liner co-ordinate system
p clock cycles for p bit of precision
Applications: Matrix transforms , Decimal to binary, SVD etc.

X
Conventional CORDIC
equations
X

Y
Y
Residue angle:
Wi
Super-CORDIC
Input angle range: 0 to /4

p bits of input angle is divided into n sets of e.g: = 250, p=24 and n=4
p/n bits = (25/90)*224
Sets : Wi ; = 0x 471C72 (Hex)
Set weight:
Angle mapping:
Parallel rotations will be performed in all sets
For n=1 , Super CORDIC and Conventional
CORDIC are same
A. Rotation Direction and Angle Determination

Each iteration involves multiple steps

Double rotations are used

W = 43.7850

i=2
2-2 <= (43.785/180) < 2-1
0.25 < 0.2432<= 0.5 (not
j iteration would make Wn-j to zero satisfying)

n iterations for required output


i=3
Direction of rotation by sign bit of Wn-j 0.125 <= 0.2432 < 0.25
(satisfying)
Overflow handling at the end of each
iteration
B. Scaling compensation

Algorithm performs rotation for subset of angles


Iteration 1 (j=0),p =
24, n= 4
R [0,5]
seudo code for Super-CORDIC architecture

Input angle (W) P bits

Angle
mapping
(P/n )+k
W3 W2 W1 W0 bits

0 W2 W1 W0 iter 1

0 0 W1 W0 iter 2
W
0 0 0 iter 3
0

0 0 0 0 iter 4
Results
Table 1: Super-CORDIC rotations for p = 24, n = 4 and input angle 250
Iteration Residual Angle W3 W2 W1 W0 Rotation
(W)
Initial 0x 471C72 0x11 0x31 0x31 0x32
Iteration 1 0x1F2F91 0x8 0x3F3 0x3FE 0x11 14.03624
0xFFF742B0 0x3FF 0x3B5 0x3CB 0x3F0 14.03624
0xFFF9CE88 0x3FF 0x3DD 0x3FA 0x8 -0.89517
0xFFFC5A60 0 0x3C5 0x29 0x20 -0.89517

Iteration 2 0xFFFEE638 0 0x3EE 0x18 0X38 - 0.89517


0x2C29 0 0x3 0x3EF 0X69 -0.44761
0x36B 0 0 0xD 0X2B 5.59528e-2

Iteration 3 0xE0 0 0 0x3 0x20 3.49705e-3


0x3E 0 0 0 0x3E 8.74264e-4
Iteration 4 0x16 0 0 0 0x16 2.18566e-4
0x2 0 0 0 0x2 1.09283e-4
0 0 0 0 0 1.36603e-5
p/n = 4 n=4

For a constant value of p/n,


p = 24 increasing
the number of precision bits p, does
not do much benefit
p = 24 shows the minimum error
n = 4 shows the minimum error
Conclusion

Reduces the iterations to (p/n)+1


The hardware cost is lower than the other redundant CORDIC
systems
Thank You

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