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Address Bus
CPU
Bus Serial
4 I/O Ports
OSC Control Port
P0 P1 P2 P3 TxD RxD
Address/Data
Pin Description of the 8051
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 8051 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7
(8031) 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
Pins of 8051 1/4
Vcc pin 40
Vcc provides supply voltage to the chip.
The voltage source is +5V.
GND pin 20 ground
XTAL1 and XTAL2 pins 19,18
Figure (a). XTAL Connection to 8051
C2
XTAL2
30pF
C1
XTAL1
30pF
GND
Pins of 8051 2/4
10 uF 31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST
Pins of 8051 3/4
Vcc
10 K
P0.0
DS5000 P0.1
Port 0
P0.2
8751 P0.3
8951 P0.4
P0.5
P0.6
P0.7
Port 3 Alternate Functions
P3 Bit Function Pin
P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17
RESET Value of Some 8051 Registers:
R0
DPH DPL DPTR
R1
R2
PC PC
R3
R5
R6
R7
7FH
30H
2FH
Bit-Addressable RAM
20H
1FH Register Bank 3
18H
17H Register Bank 2
10H
0FH Register Bank 1( Stack)
08H
07H Register Bank 0
00H
8051 Flag bits and the PSW register
CY AC F0 RS1 RS0 OV -- P
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH
Addressing Modes
Immediate
Register
Direct
Register Indirect
Indexed
Immediate Addressing Mode
MOV A,#65H
MOV A,#A
MOV R6,#65H
MOV DPTR,#2343H
MOV P1,#65H
Register Addressing Mode
MOV Rn, A ;n=0,..,7
ADD A, Rn
MOV DPL, R6
MOV DPTR, A
MOV Rm, Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be acces sed using direct addressing mode, it is most often used to acce ss RAM loc. 30 7FH.
MOV A,@Ri ; move content of RAM loc. Where address is held by Ri into A
( i=0 or 1 )
MOV @R1,B
In other word, th e conten t of register R0 or R1 is sources or target in MOV, ADD and SUBB in structions.
Example: Write a program to copy a block of 10 b ytes from RAM location starting at 40H to RAM location starting at 60H.
Solution:
MOV R0,#40H ; source pointer
MOV R1,#60H ; destination pointer
MOV R2,#10 ; counter
B ACK: MOV A,@R0
MOV @R1,A
INC R0
INC R1
DJNZ R2,BACK
Indexed Addressing Mode And On-Chip ROM Access
This mode is widely used in accessing data elements of look-up table entries located in the program (code) space ROM at the 8051
MOVC A,@A+DPTR
A= content of address A +DPTR from ROM
Note:
Because the data elements are stored in the program (code ) space ROM of the 8051, it uses the instruction MOVC instead of MOV. The C means code.
SJMP and LJMP:
LJMP(long jump)
LJMP is an unconditional jump. It is a 3-byte instruction in which the first byte is the op-code, and the second and third bytes represent the 16-bit address of the target location. The 20byte target address allows a jump to any memory location
from 0000 to FFFFH.
SJMP(short jump)
In this 2-byte instruction. The first byte is the op-code and the second byte is the relative address of the target location. The relative address range of 00-FFH is divided into forward and backward jumps, that is , within -128 to +127 bytes of
memory relative to the address of the current PC.
MUL & DIV
MUL AB ;B|A = A*B
MOV A,#25H
MOV B,#65H
MUL AB ;25H*65H=0E99
;B=0EH, A=99H
DIV AB ;A = A/B, B = A mod B
MOV A,#25H
MOV B,#10H
DIV AB ;A=2, B=5
Rotate
EXAMPLE:
RR:
RRC:
RL:
RLC:
C
ACALL: Absolute Call JC: Jump if Carry Set PUSH: Push Value Onto Stack
ADD, ADDC: Add Acc. (With Carry) JMP: Jump to Address RET: Return From Subroutine
AJMP: Absolute Jump JNB: Jump if Bit Not Set RETI: Return From Interrupt
ANL: Bitwise AND JNC: Jump if Carry Not Set RL: Rotate Accumulator Left
CJNE: Compare & Jump if Not Equal JNZ: Jump if Acc. Not Zero RLC: Rotate Acc. Left Through Carry
CLR: Clear Register JZ: Jump if Accumulator Zero RR: Rotate Accumulator Right
DIV: Divide Accumulator by B MOVC: Move Code Memory SUBB: Sub. From Acc. With Borrow
DJNZ: Dec. Reg. & Jump if Not Zero MOVX: Move Extended Memory SWAP: Swap Accumulator Nibbles
JBC: Jump if Bit Set and Clear Bit ORL: Bitwise OR XRL: Bitwise Exclusive OR
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
ANL A,Rn
Logical instructions:
ORL A,#Data
ANL A,Direct ORL Direct,A
ANL A,@Ri ORL Direct,#Data
ANL A,#Data XRL A,Rn
ANL Direct,A XRL A,Direct
ANL Direct,#Data XRL A,@Ri
ORL A,Rn XRL A,#Data
ORL A,Direct XRL Direct,A
ORL A,@Ri XRL Direct,#Data
CLR A
Logical instructions:
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
MOV A,Rn
Data transfer instructions:
MOV Direct, Direct
MOV A, Direct MOV Direct,@Ri
MOV A,@Ri MOV Direct,#Data
MOV A,#Data MOV @Ri,A
MOV Rn,A MOV @Ri,Direct
MOV Rn,Direct MOV @Ri,#Data
MOV Rn,#Data MOV DPTR,#Data16
MOV Direct,A MOVX A,@Ri
MOV Direct, Rn MOVX A,@DPTR
PUSH Direct
Data transfer instructions:
POP Direct
XCH A,Rn
XCH A, Direct
XCH A,@Ri
XCHD A,@Ri
MOVX @Ri,A
MOV @DPTR,A
CLR C
Boolean Variable Manipulation instructions:
ORL C,/bit
CLR bit MOV C,bit
SETB C MOV bit,C
SETB bit JC rel
CPL C JNC rel
CPL bit JB bit,rel
ANL C,bit JNB bit,rel
ANL C,/bit JBC bit,rel
ORL C,bit
ACALL addr11
Program branching instructions:
JNZ rel
LCALL addr16 CJNE A,direct,rel
RET CJNE A,#data,rel
RETI CJNE Rn,#data,rel
AJMP addr11 CJNE @Ri,#data,rel
LJMP addr16 DJNZ Rn,rel
SJMP rel DJNZ direct,rel
JMP @A+DPTR NOP
JZ rel
TIMERS
The 8051 has two timers:
1. TIMER 0
2. TIMER 1
TIMER 0
TIMER 1
TMOD
Register