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Health minutes
0.1 Mbps
monitoring
Smart cities,
Surveillance, 100 Mbps seconds
Interaction
Autonomous driving
1000 Mbps milliseconds
& Tactile Internet
Sensing and processing requirements
Biometrics
16 Kbps Latency: 10s to 100s of milliseconds
0.08 Kbps
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IcySOC RTD 2013
ULP Imager
EMG/ECG/EEG
Idle: ~1 uW
100 uW 2 mW 1 10 mW
Active: ~ 50 mW
L. Benini
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IcySOC RTD 2013
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IcySOC RTD 2013
Search
Key Kernels Filters DCT/FFT
Algorithms
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IcySOC RTD 2013
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IcySOC RTD 2013
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IcySOC RTD 2013
Less susceptible to variation with New 6-T and 7-T bit-cell Robust ultra-low voltage
proper transistor sizing structures for reliable sub-VT memory for any technology,
Low leakage for energy efficiency operation including FDSOI with BB
Low leakage in sub-VT operation Lower energy than SRAM
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IcySOC RTD 2013
Designed and
manufactured
in Switzerland
IcySoC custom cells and memories enable Exploiting the full potential of new technologies:
operation down to 0.37V for leading FDSOI body bias compensates for variability
energy efficiency: 17.1pJ/cycle @ 19kHz at near-threshold voltages and reduces leakage
with leakage as low as 2.8 nW at 0.48 V Standard-cell memories with reconfigurable
Energy-autonomous operation memory maps enable ULP operation for a wide
from Photo-Voltaic Supply voltage range
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IcySOC RTD 2013
Use the potential of trading-off accuracy and speed to partially compensate for performance loss due to
voltage scaling
Approximation allows to tolerate a certain amount of circuit failures due to reliability issues reduce
overhead for worst-case design
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IcySOC RTD 2013
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IcySOC RTD 2013
20-50% power-area savings on image applications Key application kernels show gains of up to
5.54x in energy efficiency (1.71x on average)
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IcySOC RTD 2013
Exploits data dependencies Careful balance between Avoid overhead for 100% reliable operation
of power consumption for false-alarm and missed in processors and memories
>40% power reduction events: 80% power reduction 20 80 % power savings
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IcySOC RTD 2013
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