KE16403 Logic Design

Lecture 17: Latches

 Learning Outcomes
Derive characteristic equation for latches
Draw a timing diagram for latches
Construct latches from Gates
Sketch Asynchronous State Transition
Diagram for latches

Readings 11.1 11.3

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General digital system
diagram

3
 Properties of sequential
circuits
combinational logic
the outputs of the circuit depend only on the current values of
the input variables
sequential logic circuits
the outputs can depend on the present and past values of the
inputs and the outputs
At any moment in time, a sequential circuit exists in one
of a number of predetermined states
it moves through a defined sequence of transitions from one
state to the next
the output variables are used to describe the state of a
sequential circuit, either directly or through derived state
variables
Example: Counter

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 Synchronous and
asynchronous
Synchronous sequential logic:
the time at which transitions between circuit states occurs
is controlled by a common clock signal
changes in all variables occur simultaneously
Asynchronous sequential logic:
state transitions occur independently of any clock, and
normally depend on the time at which input variables
change
outputs do not necessarily change simultaneously
Clock
a clock signal is a square wave of a fixed frequency
it is used to trigger state transitions at fixed times in
synchronous circuits

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 Flip-flops and latches
Flip-flops and latches are the fundamental elements of
sequential circuits
bistable (two stable states)
Flip-flops and latches are essentially 1-bit storage devices
outputs can be set to store either 1 or 0 depending on the inputs
even when the inputs are deasserted, the outputs retain their
prescribed values
Flip-flops and latches (normally) have 2 complementary
outputs
usually denoted Q and Q
Three main types:
R-S, J-K, D-type

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A NOR gate S-R latch

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 Asynchronous State Transition
Diagram
SR=00 SR=00
SR=01 SR=10
SR=10
QQ' QQ'
01 10
SR=01

SR=11 SR=11
SR Latch:
QQ'
SR=01 00 SR=10 SR Q
SR=00
00 hold
01 0
? 10 1
11 indeterminate
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Characteristic Equation

Qnext = Q+ = S + RQ

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Nand-gate based SR latch

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A S-R latch built from NAND
gates

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S-R latch to debounce a
switch

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 Data (D) Latch
Data latch eliminate, the need for
complementary inputs
Outputs are also complementary

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D latch timing

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