CSE241A

VLSI Digital Circuits

Winter 2003

Recitation 5: File
Formats

CSE241 Formal Verification.1 Cichy, UCSD 2003

 LEF - Explained
Library - Physical
Library Exchange Format (LEF)
- Physical characteristics of the technology library
Abstracts of the standard cell library (ie. TSMC .18u)
Abstracts of all blocks and IO cells
Includes layer, via, placement site type
- Timing characteristics of the technology library
Contains timing models for each pin of each component of the
library

CSE241 Formal Verification.2 Cichy, UCSD 2003

 Example LEF
NAMESCASESENSITIVE OFF ;
#TECHNOLOGY SECTION

LAYER MET1
TYPE ROUTING ;
PITCH 3.5 ;
WIDTH 1.2 ;
SPACING 1.4 ;
DIRECTION HORIZONTAL ;
RESISTANCE RPERSQ .7E-01 ;
CAPACITANCE CPERSQDIST .46E-04 ;
END MET1

LAYER VIA
TYPE CUT ;
END VIA

LAYER MET2
TYPE ROUTING ;
PITCH 4 ;
WIDTH 1.8 ;
SPACING 1.4 ;
DIRECTION VERTICAL ;
RESISTANCE RPERSQ .35E-01 ;
CAPACITANCE CPERSQDIST .31E-04 ;
END MET2

CSE241 Formal Verification.3 Cichy, UCSD 2003

 DEF Explained

Design - Physical
Design Exchange Format (DEF)
- Physical characteristics of the cells
Macros of design
Placement information
Pin locations
Metal blockages
Orientation

CSE241 Formal Verification.4 Cichy, UCSD 2003

 DEF
DEF
Contains the design-specific information of a circuit and is a
representation of the design at any point during the layout process
DEF file is an ASCII representation S
Syntax conventions conveys logical design data to, and physical design
data from, place-and-route tools
Can include internal connectivity grouping information, and physical
constraints
Physical:
- Placement locations and orientations
- Routing geometry data
- Logical design changes for backannotation.
Place-and-route tools can read physical design data
- For performing ECO changes
Clock gen
Optimization
SI based
Floorplan
- ROWS, TRACKS, GCELLGRID, and DIEAREA
CSE241 Formal Verification.5 Cichy, UCSD 2003
 DEF Structure
Standard DEF files can contain the following statements and sections. You
must specify the statements and sections in the following order.
..
VERSION statement
[ GCELLGRID
NAMESCASESENSITIVE statement ]...
statement
[ VIAS statement ]
DIVIDERCHAR statement
[ REGIONS statement ]
BUSBITCHARS statement COMPONENTS section
DESIGN statement [ PINS section ]
[ TECHNOLOGY statement [ PINPROPERTIES
] section ]
[ UNITS statement ] [ BLOCKAGES section ]
[ HISTORY statement ]... [ SLOTS section ]
[ FILLS section ]
[ PROPERTYDEFINITIONS
section ] [ SPECIALNETS section ]
[ DIEAREA statement ] NETS section
[ SCANCHAINS section ]
[ ROWS statement ] ...
[ GROUPS section ]
[ TRACKS statement ]... [ BEGINEXT section ]
.. END DESIGN statement
CSE241 Formal Verification.6 Cichy, UCSD 2003
 Example DEF

PROPERTYDEFINITIONS

DESIGN HSNAPGRID STRING "-1653120 1120 2954" ;

DESIGN VSNAPGRID STRING "-1653960 1320 2508" ;
DESIGN VERILOGDESIGNNAME
STRING "cds_vbin.aes_cipher_cores_top_2:hdl" ;
DESIGN GCFLIBRARY_TIMESTAMP STRING "1045714484" ;
DESIGN GCFLIBRARY STRING "../gcf_out" ;

END PROPERTYDEFINITIONS
DIEAREA ( -1653960 -1653120 ) ( 1655280 1654240 ) ;

ROW ROW_168 tsm3site -852720 842240 N DO 1293 BY 1 STEP 1320 0 ;

ROW ROW_167 tsm3site -852720 832160 FS DO 1293 BY 1 STEP 1320 0 ;
ROW ROW_166 tsm3site -852720 822080 N DO 1293 BY 1 STEP 1320 0 ;
ROW ROW_165 tsm3site -852720 812000 FS DO 1293 BY 1 STEP 1320 0 ;
CSE241 Formal Verification.7 Cichy, UCSD 2003