ECE 4121

VLSI Design
Semester II 2005-2006

Lecture 01:
Introduction
AHM Zahirul Alam ( http://staff.iiu.edu.my/zahirulalam)

ECE 4121 VLSI Design

 Course Structure
Lectures:
2 weeks on the CMOS inverter
3 weeks on static and dynamic CMOS gates
2 weeks on C, R, and L effects
2 week on sequential CMOS circuits
2 weeks on design of datapath structures
2 weeks on memory design
1 week on design for test, margining, scaling, trends

ECE 4121 VLSI Design

 Executives might make the final decisions about what
would be produced, but engineers would provide most
of the ideas for new products. After all, engineers were
the people who really knew the state of the art and who
were therefore best equipped to prophesy changes in
it.
The Soul of a New Machine, Kidder, pg 35

ECE 4121 VLSI Design

 From

1945
ENIAC filled an entire room!
17,468 vacuum tubes,
70,000 resistors, and
10,000 capacitors
6,000 manual switches
and many blinking lights!
Could add 5,000 numbers in
a single second
ECE 4121 VLSI Design
 To

1947
point-contact transistor
1954
first computer with no tube
800 transistors and
10,000 germanium crystal rectifiers
only 100 watts
1958
Invention of the Integrated Circuit

ECE 4121 VLSI Design

 Transistor Revolution

Transistor Bardeen (Bell Labs) in 1947

Bipolar transistor Schockley in 1949
First bipolar digital logic gate Harris in 1956
First monolithic IC Jack Kilby in 1959
First commercial IC logic gates Fairchild 1960
TTL 1962 into the 1990s
ECL 1974 into the 1980s

ECE 4121 VLSI Design

 MOSFET Technology
MOSFET transistor - Lilienfeld (Canada) in 1925 and
Heil (England) in 1935
CMOS 1960s, but plagued with manufacturing
problems
PMOS in 1960s (calculators)
NMOS in 1970s (4004, 8080) for speed
CMOS in 1980s preferred MOSFET technology
because of power benefits
BiCMOS, Gallium-Arsenide, Silicon-Germanium
SOI, Copper-Low K,

ECE 4121 VLSI Design

 Moores Law
In 1965, Gordon Moore predicted that the number of
transistors that can be integrated on a die would double
every 18 to 14 months (i.e., grow exponentially with
time).
Amazingly visionary million transistor/chip barrier was
crossed in the 1980s.
2300 transistors, 1 MHz clock (Intel 4004) - 1971
16 Million transistors (Ultra Sparc III)
42 Million, 2 GHz clock (Intel P4) - 2001
140 Million transistor (HP PA-8500)

ECE 4121 VLSI Design

 Microprocessors

Intel 80286: 16-bit microprocessor - 52,000 transistors

Intel 80386: 32-bit CISC(1989) - 1M transistors (1um CMOS technology)
Intel 80486: 32-bit CISC (1990) - 1.2M transistors (1um CMOS technology)
Intel Pentium: 64-bit CRISC (1993) - over 3M transistors (0.8um BiCMOS
technology)
Intel Pentium II : 64-bit CRISC (1997)
- 7.5M transistors ( 0.35um ~ 0.25um BiCMOS technology)
Intel Pentium III : 64-bit CRISC (1999)
- 9.5M transistors ( 0.25um BiCMOS technology)
Intel Pentium IV : 64-bit NetBurst micro-architecture (2002)
- 55M transistors (0.13um technology) uses 1.475 Volt
2.4 GHz clock,

ECE 4121 VLSI Design

 Intel 4004 Microprocessor

ECE 4121 VLSI Design

 Intel Pentium (IV) Microprocessor

ECE 4121 VLSI Design

 State-of-the Art: Lead Microprocessors

ECE 4121 VLSI Design

 Moores Law in Microprocessors
Transistors on lead microprocessors double every 2 years

1000

100 2X growth in 1.96 years!

Transistors (MT)

10
P6
Pentium proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
ECE 4121 VLSI Design Courtesy, Intel
 Moores Law is alive and well

ECE 4121 VLSI Design

 Evolution in DRAM Chip Capacity
human memory
human DNA

4X growth every 3 years! 0.07 m

0.1 m

0.13 m

book 0.18-0.25 m

0.35-0.4 m

0.5-0.6 m

0.7-0.8 m
encyclopedia
2 hrs CD audio
1.0-1.2 m 30 sec HDTV
1.6-2.4 m

page

ECE 4121 VLSI Design

 Die Size Growth
Die size grows by 14% to satisfy Moores Law

100
Die size (mm)

P6
486 Pentium proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year
ECE 4121 VLSI Design Courtesy, Intel
 Clock Frequency
Lead microprocessors frequency doubles every 2 years

10000

1000 2X every 2 years

Frequency (Mhz)

P6
100
Pentium proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
ECE 4121 VLSI Design Courtesy, Intel
 Power Dissipation

Lead Microprocessors power continues to increase

100

P6
Pentium proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Power delivery and dissipation will be prohibitive

ECE 4121 VLSI Design Courtesy, Intel

 Power Density
10000
Rocket
Nozzle
Power Density (W/cm2)

1000

Nuclear
100 Reactor

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

Power density too high to keep junctions at low temp

ECE 4121 VLSI Design Courtesy, Intel

 Design Productivity Trends
Logic Transistor per Chip (M) 10,000 100,000

1,000 Logic Tr./Chip 10,000

Tr./Staff Month.

(K) Trans./Staff - Mo.

100 1,000
Complexity

Productivity
10 58%/Yr. compounded 100
Complexity growth rate

1 10

x x
0.1 1
xx
x
21%/Yr. compound
x x
x Productivity growth rate
0.01 0.1

0.001 0.01
1989

1997

2001
1991

1993

1995

1999

2003

2005
1987

2007
1981

1983
1985

2009
Complexity outpaces design productivity

ECE 4121 VLSI Design Courtesy, ITRS Roadmap

Technology Directions: SIA Roadmap

Year 1999 2002 2005 2008 2011 2014

Feature size (nm) 180 130 100 70 50 35
Mtrans/cm2 7 14-26 47 115 284 701
Chip size (mm2) 170 170-214 235 269 308 354
Signal pins/chip 768 1024 1024 1280 1408 1472
Clock rate (MHz) 600 800 1100 1400 1800 2200
Wiring levels 6-7 7-8 8-9 9 9-10 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6
High-perf power (W) 90 130 160 170 174 183
Battery power (W) 1.4 2.0 2.4 2.0 2.2 2.4
For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999
doubling every two years)

http://www.itrs.net/ntrs/publntrs.nsf

ECE 4121 VLSI Design

 Why Scaling?

Technology shrinks by ~0.7 per generation

With every generation can integrate 2x more functions on
a chip; chip cost does not increase significantly
Cost of a function decreases by 2x
But
How to design chips with more and more functions?
Design engineering population does not double every two years

Hence, a need for more efficient design methods

Exploit different levels of abstraction

ECE 4121 VLSI Design

 Design Abstraction Levels

SYSTEM

MODULE
+

GATE

CIRCUIT
Vin Vout

DEVICE
G
S D
n+ n+

ECE 4121 VLSI Design

 Major Design Challenges
Microscopic issues Macroscopic issues
ultra-high speeds time-to-market
power dissipation and design complexity
supply rail drop (millions of gates)
growing importance of high levels of
interconnect abstractions
noise, crosstalk reuse and IP, portability
reliability, manufacturability systems on a chip (SoC)
clock distribution tool interoperability

Year Tech. Complexity Frequency 3 Yr. Design Staff Costs

Staff Size
1997 0.35 13 M Tr. 400 MHz 210 $90 M
1998 0.25 20 M Tr. 500 MHz 270 $120 M
1999 0.18 32 M Tr. 600 MHz 360 $160 M
2002 0.13 130 M Tr. 800 MHz 800 $360 M
ECE 4121 VLSI Design
 Semi-Custom

Design with Pre-Designed Building Blocks

(Standard Cell)
- Low Level Design
+Minimized Needed IC Design Skills

Uses Pre-Implemented Layout (Gate Array)

+Pre-Characterized and Tested
+Minimize Tooling
- Density Sacrifice

ECE 4121 VLSI Design

 Full Custom

Until Recently, Unthinkable

Expensive Development
Risky
Special Skills
Lack of Manpower
Justified in Only the Most Desperate Cases

ECE 4121 VLSI Design

 IC Economics

Die Size
Pin Count
Package
Process
Functional Density

ECE 4121 VLSI Design

 Process Selection Criteria

Speed
Power
Availability
Tooling Cost
Production Cost
Turnaround Time

ECE 4121 VLSI Design

 VLSI Design

Managing Complexity
Simplify the design problem
Cant understand 10M transistors, or 100M rectangles
Need to make less complex (and less numerous) models

Abstraction
Simplified model for a thing, works well in some subset of the design space

Constraints
Needed to ensure that the abstractions are valid
Might work if you violate constraints, but guarantees are off

Understand the underlying technology

Provide a feeling for what abstractions and constraints are needed
Determine efficient solutions (in design time, or implementation
area, power, or performance )

ECE 4121 VLSI Design

 Abstractions and Disciplines
How to Deal with 107 Transistors

Digital abstraction Constrain the design space to

signals are 1 or 0 simplify the design process

Switch abstraction strike a balance between design

MOSFETs as simple switches complexity and absolute performance

Gate abstraction
Unidirectional elements
Separable timing Partition the problem(Use hierarchy)

Synchronous abstraction Module is a box with pins

Race free logic apply recursively

Function does not depend on

timing
ECE 4121 VLSI Design
 Design Levels

Specification Circuit
what the system (or component) transistor circuits to realize

is supposed to do logic elements

Device
Architecture
behavior of individual circuit
high- level design of component
state defined
elements
logic partitioned into major blocks Layout

Logic geometry used to define and

connect circuit elements
gates, flip-flops, and the
Process
connections between them
steps used to define circuit
elements
Can describe design at many different levels of abstraction
High- lighted levels we will discuss in this class
ECE 4121 VLSI Design
 VLSI Design Process

ECE 4121 VLSI Design

 VLSI Design Process

ECE 4121 VLSI Design

The VLSI Design Process

ECE 4121 VLSI Design

The VLSI Design Process

ECE 4121 VLSI Design

 The Hard Part

A real design will have at least 1 million polygons and 100K

transistors
Mistakes are really expensive
A full set of masks for 0.13 is about $600,000
Any single error in any of the polygons can ruin the chip
No one person can really comprehend 1 million of anything
Much less 1 billion
Need to attack the problem with the standard engineering tools
Hierarchy and abstraction
Design reuse
Computer automation

ECE 4121 VLSI Design

 Levels of Design Abstraction
Consider entire design
at top levels only
Increasing amounts of
automation possible further
down the stack

ECE 4121 VLSI Design

 Design Methodologies and Flows
Left fork: Full custom
design flow
Center fork: ASIC flow
Right fork: System on Chip
(SOC) flow

ECE 4121 VLSI Design

 Full Custom Design Flow

Has the best performance

Is the most labor intensive

ECE 4121 VLSI Design

 Schematic Capture/Simulation
Circuit drawn at transistor,
gate, and block level
Blocks can be recursively
placed inside one another
Utility programs produce
netlists for simulation tools

ECE 4121 VLSI Design

 Layout
Draw and place transistors for all
devices in schematic
Rearrange transistors to
minimize interconnect length
Connect all devices with routing
layers
Possible to place blocks within
other blocks
Layout hierarchy should
match schematic hierarchy

ECE 4121 VLSI Design

 Design Rule Checking (DRC)
Fab has rules for relationships between polygons in
layout
Required for manufacturability
DRC checker looks for errors
width
space
enclosure
overlap
Violations flagged for later fixup

ECE 4121 VLSI Design

 Layout Versus Schematic (LVS)
Extracts netlist from layout
by analyzing polygon
overlaps
Compares extracted netlist
with original schematic
netlist
When discrepancies occur,
tries to narrow down
location

ECE 4121 VLSI Design

 Layout Parasitic Extraction (LPE)

Estimates capacitance between structures in the layout

Calculates resistance of wires
Output is either a simulation netlist or a file of interblock
delays

ECE 4121 VLSI Design

 ASIC Design Flow
Separate teams to
design and verify
Physical design is
(semi-) automated
Loops to get device
operating frequency
correct can be
troubling

ECE 4121 VLSI Design

 Register Transfer Level (RTL)

Sections of combinational Goo separated by timing

statements
Defines behavior of part on every clock cycle boundary

ECE 4121 VLSI Design

 Logic Synthesis
Changes cloud of combinational
functionality into standard cells
(gates) from fab-specific library
Chooses standard cell flip-flop/
latches for timing statements
Attempts to minimize delay and
area of resulting logic

ECE 4121 VLSI Design

 Standard Cell Placement and Routing

Place layout for

each gate
(cell) in design
into block
Rearrange cell
layouts to
minimize routing
Connect up cells

ECE 4121 VLSI Design

 System on Chip Design Flow
Can buy Intellectual Property (IP) from various vendors
Soft IP: RTL or gate level description
Synthesize and Place and Route for
your process.
Examples: Ethernet, MAC, USB
Hard IP: Polygon level description
Just hook it up
Examples: XAUI Backplane driver,
embedded DRAM
Also: Standard cell libraries for ASIC flow

ECE 4121 VLSI Design

 Chip Assembly
Integrate blocks from previous steps into final layout
Early floorplanning is key

ECE 4121 VLSI Design

 Tapeout
Used to write 9-track computer tapes for mask making
Now, Transfer polygons to fabrication company via ftp
Youre done! (Except for documentation, test, vector
generation, device bringup, skew lots, reliability tests,
burnin)

ECE 4121 VLSI Design