Slide 5 - Introduction To Digitial Circuits

Introduction to Digital
Circuits
1
Digital System
The basic AND, OR and NOT gates can be
combined in a huge variety of ways to build the
digital circuitry that drives modern computers.
2
Multilevel NAND Logic
NAND can function as either a NAND or a
negative OR because by Demorgans theorem
AB A B
NAND Negative OR
NOR can function as either a NOR or a negative

AND because by Demorgans theorem
A B A B
NOR Negative AND
3
Digital System
Universality of NAND and NOR gates
NAND & NOR are very popular logic elements

because they may be used as universal gates. That
is, they may be employed to construct an inverter,
an AND gate, an OR gate, or any combination of
these functions.
4
Digital System
NAND gates can be used to implement NOT,
AND, OR and NOR operations
NAND as Inverter
A 74LS01
A
NAND used as AND Gate
A AB AB AB
74LS01
B 74LS01
5
Digital System
NAND used as OR Gate
A A
74LS01
74LS01 A B A B
B 74LS01
NAND used as NOR Gate
A 74LS01 A A B A B
A B
74LS01 74LS01
B 74LS01
B 6
Digital System
NOR gates can be used to implement NOT,
AND, OR and NAND operations
NOR as Inverter
A A
74LS02
NOR used as OR Gate
A A B
A B
B 74LS02 74LS02
7
Digital System
NOR used as AND Gate
A
A B AB
NOR used as NAND Gate
A
AB
AB
8
B
Digital System
Two basic categories of circuits are
Combinational Circuits &
Sequential Circuits
9
Digital System
Combinational Circuits: Circuits whose
outputs depend only on the current inputs; hence
they appear to combine the inputs in some way to
produce the outputs
Sequential Circuits: Circuits whose outputs

depend on the both the current and past inputs;
hence they use the sequence of inputs over time
to determine the output.
10
Combinational Circuits
Basic Combinational Circuits are
Adder
Comparator
Code Converter
Decoder
Encoder
Multiplexer
Demultiplexer
11
Sequential Circuits
Basic Sequential circuits are
Latches
Flip Flops
Counters
Shift Registers
12
Decoders & Encoders
13
Decoders
The basic function of a decoder is to detect the
presence of a specified combination of bits (code)
on its input and to indicate that presence by a
specified output level.
In its general form, a decoder has n input lines to

handle n bits and 1 to 2n output lines to indicate
the presence of one or more n-bit combination
14
Decoders
Basic Binary Decoder
The function of the binary decoder is to determine if a
given input combination has occurred
For example, if we wish to detect that 1101 occurs on

the inputs of a digital circuit we must design a
decoder which only outputs 1 for this instance
Accordingly, a 4-input AND / NAND gate and an

Inverter may be employed as illustrated
15
Decoders
A
B
X ABC D
C
Decoder circuit for X=1101 with active HIGH output
A
B
X ABC D
C
Decoder circuit for X=1101 with active LOW output

16
Decoders
Three Bit Binary Decoder
In order to decode all possible combinations of
three bits, eight (23=8) decoding logic gates are

required.
This type of decoder is called the 3-line-to-8-line
decoder because they are 3 inputs and 8 outputs.
Logic symbol for

3-to-8 line decoder 17
Decoders
Decoding functions & truth tables for the 3-line-to-8-line decoder
Decimal Binary Logic Outputs
Digit Inputs Function
D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
2 0 1 0 0 0 1 0 0 0 0 0
3 0 1 1 0 0 0 1 0 0 0 0
4 1 0 0 0 0 0 0 1 0 0 0
5 1 0 1 0 0 0 0 0 1 0 0
6 1 1 0 0 0 0 0 0 0 1 0
7 1 1 1 0 0 0 0 0 0 0 1
18
Decoders
4-Bit Binary Decoder - Block
0
1
2
3
A 4
5
B 6
7
C 8
9
D 10
11
12
13
14
15 19
Decoders
4-Bit Binary Decoder - Logic
Sixteen decoding
Interconnection gates
A/
A A/ B/
0/
C/
A D/
A
B/
B B/ 1/
C/
D/
B A/
B
2/
C C/ C/
D/
D D/
A
D B
15/
C
D
20
Decoders
4-Bit Binary Decoder Decoding functions &
truth table
21
Decoders
The 74154 : 4-line-to-16-line decoder
1
0 2
1 3
2 4
3 5
4 6
23 5 7
22 A 6 8
21 B 7 9
20 C 8 1 0
D 9 1 1
1 0 1 3
1 1 1 4
1 2 1 5
18 1 3 1 6
19 G 1 1 4 1 7
G 2 1 5
74LS154
22
Decoders
23
Decoders
BCD-to-Decimal Decoder
The BCD-to-decimal decoder converts each BCD

code to its decimal equivalent.
It is frequently referred to as 4-line-to 10-line

decoder
24
BCD to Decimal Decoder
BCD/DEC
0
1
2
A 3
B 4
C 5
D 6
7
8
9
25
BCD to Decimal Decoder
7442A - BCD-to-Decimal Decoder
1
0 2
1 3
15 2 4
14 A 3 5
13 B 4 6
12 C 5 7
D 6 9
7 10
8 11
9
26
BCD to 7-Segment Decoder
BCD-to-7-Segment Decoder/Driver
27
BCD-to-7-Segment Decoder/Driver
Common Anode Leds
Common Cathode Leds
28
Common Cathode Interface
BCD to 7 Segment Decoder/ Driver - 74LS48
7 13
1 1 A 12
2 2 B 11
6 4 C 10
8 D 9
4 E 15
5 BI/RBO F 14
3 RBI G
LT
74LS48
29
Connection Scheme (Common
Cathode) R33 R D1
DIODE
R33 R DIODE
D1
Segement R33 R D1
DIODE
Select R33 R D1
DIODE
(Decoder R33 R D1
DIODE
Output) R33 R DIODE
D1
R33 R DIODE
D1
R33 R DIODE
D1
R35
Q1
NPN BCE
Digit R
Select
30
Common Anode Interface
BCD to 7 Segment Decoder/ Driver - 74LS47
7 13
1 1 A 12
2 2 B 11
6 4 C 10
8 D 9
4 E 15
5 BI/RBO F 14
3 RBI G
LT
74LS47
31
Connection Scheme (Common
Anode)
R33 R DIODE
D1
R33 R DIODE
D1
Segement R33 R
D1
DIODE
Select R33 R
D1
DIODE
(Decoder R33 R DIODE
D1
Output) R33 R DIODE
D1
R33 R DIODE
D1
R33 R DIODE
D1
Q5 Digit
R35 Select
R
PNP
VCC5 32
4 Digit Interface
R 7
4 BCD to
7Segment
Micro- Decoder
Controll
er
Q1 Q2 Q3 Q4
R1
R2
R3 R4
33
Encoders
An encoder is a combinational logic circuit that
performs the opposite function of the decoder
circuit.
An encoder accepts an active level (i.e. 1 or 0) on

one of its inputs representing a digit (e.g. decimal or
octal digit) and converts it to a coded output (e.g.
binary or BCD).
34
Encoders
The Decimal-to-BCD Encoder
The Decimal to BCD Encoder have 10 inputs and 4
outputs corresponding to the BCD code
The logic symbol for Decimal to BCD Encoder

35
Decimal-to-BCD Encoder
BCD Code (8421)
36
An Encoder Application
The Keyboard Encoder
The ten decimal digits on the keyboard must be

encoded for processing by a logic circuitry.
When one of the keys is pressed, the decimal digit is

encoded into the corresponding BCD code.
37
The Keyboard Encoder
+5V
R3
R2 74147 Priority Encoder
R1
1 2 3
1
2
R5 3
R6
4
5 A0
R4
6 A1
7 A2
4 5 6 8 A3
9
0 74LS145
R9
R8
R7
7 8 9
R0
0
38
Multiplexers and
Demultiplexers
39
Multiplexers (Data Selectors)
A multiplexer (MUX) is a device that accepts data
from one of many input sources for transmission
over a common shared line.
The basic multiplexer has several data input lines

and a single output line
It also has data select inputs that permits digital

data on any one of the inputs to be switched to the
output line
40
Multiplexers
1 of 4 multiplexer
Data Select Inputs Input Selected
S1 S0
0 0 D0
0 1 D1
1 0 D2
1 1 D3
41
Multiplexers
74157 Quad Two-input Multiplexer
Enable 15
4 separate 2-input EN
Data 1
G1
multiplexers on a single chipSelect 1A
1 1Y
1B 1
2A
One data select input 2Y
2B
=1 BY 3A
3Y
=0 AY 3B
4A 4Y
& One enable input 4B
42
Multiplexers
74151 4
3 D0
Eight-Input Multiplexer 2 D1
1 D2
15 D3 6
14 D4 W
13 D5
12 D6 5
D7 Y
11
10 S0
9 S1
7 S2
Enable
43
Multiplexers
Examples of Multiplexer
applications
Interfacing different inputs to a single

channel A/D converter
The seven-segment display

multiplexer
44
Multiplexers
Application
Analog
inputs
Multiplexer ADC Microcontroller
45
Multiplexers
Seven- segment display multiplexer
(common cathode)
46
Multiplexers
Logic Function Generator
A very useful application of multiplexer is in the
generation of combinational logic functions in
SOP form
For eg: 74151A (8 input mux.) can be used to

implement any specified three variable logic
function by connecting the variables to the data
select inputs and setting each data input to the
logic level required in the truth table for that
function
47
Multiplexers
48
Multiplexers
VCC
D0
D1
D2
D3
D4 W
D5
D6
D7 Y
A
B S0
C S1
S2
Enable
49
Multiplexers
If implemented with discrete logic gates, would
require as many as
Four 3-input AND gates

One 4-input OR gate and
Three inverters
50
Demultiplexers (Data Distributors)
A demultiplexer (DMUX) is a device which essentially
performs the opposite operation to the MUX.
That is, it functions as an electronic switch (data

distributor) to route an incoming data signal to one
of several outputs.
51
Demultiplexers
1 to 4 demultiplexer
Address Outputs
Data S1 S0 Y0 Y1 Y2 Y3
D 0 0 D 0 0 0
D 0 1 0 D 0 0
D 1 0 0 0 D 0
D 1 1 0 0 0 D
52
Demultiplexers
Data input
Y
0
Y
1
Y
2
Y
3
53
74154 as a Demultiplexer
Demultiplexers
74154 is a 4 to 16 decoder
Can be also used in demultiplexing

applications
In demultiplexing application the input

lines are used as the data select lines
One of the enable input is used as the data

input line with the other enable input held
LOW.
54
Demultiplexers
DMUX 1
74154 as a Demultiplexer 0 2
1 3
2 4
3 5
4 6
23 5 7
22 S0 6 8
S1 7
Select lines 21
S2 8
9
20 10
S3 9 11
10 13
11 14
12 15
13
Data In 18
G1 14
16
19 17
G2 15
55
Sequential Circuits
Latches and Flip Flops
56
Sequential Circuits
For sequential circuits, the output depends on
the sequence of inputs.
In most cases, the inputs are sequenced by

connecting one or more of the outputs to the
inputs of the circuit creating what is known as
feedback.
With feedback, the state of the circuit becomes

time dependent.
57
Sequential Circuits
Block Diagram
58
Sequential Circuits
Basic Sequential circuits are
Latches
Flip Flops
Counters
Shift Registers
59
Latches
A latch is a bistable multivibrator device that
can store one bit (0 or 1) of data
S-R latch (Set-Reset Latch)

Two inputs (S & R)
One true outputQ(0 )
One complemented output
( Q0 )
60
S-R Latch
Logic symbol
Active HIGH Active LOW

input S-R latch input S-R latch
61
S-R Latch
Active HIGH Active LOW

input S-R latch input S-R latch
62
S-R Latch
Active LOW input S-R
latch
G1
G2
When Q output is HIGH, the latch is in SET state and

when the Q output is LOW the latch is in RESET state.
Both outputs ( ) are compliment of each other
63
S-R Latch
The four modes of basic latch
operation
SET
RESET
No Change
Invalid
64
S-R Latch
Truth Table for active LOW input S-R latch
65
S-R Latch
Active HIGH input S-R latch
(similar but requires the use of opposite logic
levels)
66
S-R Latch
Truth Table for active HIGH input S-R
latch
67
S-R Latch Application
Latch as a contact- bounce eliminator
Initially, key to A
Pin1,2=0 Q=1
Pin3,4=1
68
S-R Latch Application
Initially, key to A
Pin1,2=0 Q=1
Pin 3,4=1
Key is released from A and not yet connected
to B
Pin1=1 Pin2=0 Q=1
Pin 3,4=1
Key connected to B
Pin1,2=1 Q=0
Pin 3,4=0
69
Gated S-R Latch
Gated S-R Latch
The gated latch has an enable input
(Output status determined by S&R if EN=1. S=R=1 is
invalid in the below circuit)
S
Q
EN
Q
R
70
Gated D Latch
Gated D Latch
This differs from S-R latch in that it has only one
input (D input) in addition to EN.
D
Q
EN
71
Gated D Latch
When D and EN are HIGH, the latch is SET
When D is LOW and EN is HIGH, the latch will
RESET
The 7475 Four bit latches

Four latches on a single chip
Each EN is shared by two latches
72
Gated D Latch
73
Flip Flops
Flip Flops
Flip-flops are synchronous bistable storage devices
capable of storing one bit.
The output changes are synchronised with the clock
signal.
Difference b/w latch and flip-flops is the method

used to change their states.
Latches are level triggered
Flip-flops are edge triggered (rising or falling
edge) 74
Flip Flops
Three basic edge triggered flip flops
are
S-R
D
J-K
75
Flip Flops
Logic Symbols for S-R flip-flop
(a) rising edge triggered (b) falling edge

triggered
76
Flip Flops
Logic Symbols for D flip-
flop
(a) rising edge triggered (b) falling edge

triggered 77
S-R Flip Flops
Logic Symbol Truth Table
(rising edge triggered)
78
S-R Flip Flops
Wave forms with given inputs. Assume Q is HIGH
initially
79
S-R Flip Flops
S and R are called the synchronous inputs because
data on these inputs are transferred to flip flops
output only on the triggering edge of the clock
pulse
The operation and truth table for a negative edge

triggered S-R flip flop are the same as those for a
positive except that the falling edge of the clock
pulse is the triggering edge.
80
D Flip Flops
Logic symbol Truth table
81
J-K Flip Flops
J-K Flip flops
Most widely used flip flops
Identical to S-R flip flop
But no invalid state
For J=K=1, the output toggles
Logic symbol
82
J-K Flip Flops
J
G1 Q
G3
Pulse
C transition
detector
G4
Q
K G2
83
J-K Flip Flops
Truth Table
J K C Q Operation
0 0 Rising Hold (no

edge change)
0 1 Rising 0 1 Reset
edge
1 0 Rising 1 0 Set
edge
1 1 Rising Toggle
edge 84
J-K Flip Flops
Waveforms
85
Flip Flops with Asynchronous Inputs
The inputs labeled preset (PRE) and clear (CLR)
are asynchronous inputs
These inputs can set or reset the flip flop
independent of the status of the clock signal
An active level on the preset will SET (1) the flip-
flop, similarly an active level on the clear will
RESET (0) the flip-flop.
These inputs must both be kept inactive (HIGH) for
synchronous operation
86
J-K flip flop with preset and clear
These inputs are connected such that they override the effe
of synchronous inputs J, K and the clock
87
J-K flip flop with preset and clear
(with J & K kept HIGH)
88
Pulse Triggered (Master-Slave)
Pulse Triggered (Master-Slave) Flip
flops
These flip-flops are constructed from two
separate flip-flops.
The term pulse-triggered means that data are

entered into the flip-flop on the leading edge of
the clock pulse, but the output does not reflect
the input state until the trailing edge of the
clock pulse
89
Pulse Triggered (Master-Slave)
Master-Slave S-R Flip flop logic
circuit
==
90
Pulse Triggered S-R Flip Flop
Logic diagram
91
Pulse Triggered S-R Flip Flop
Master- Slave S-R Flip flop
waveform
92
Flip Flops Operating
Characteristics
Operating Characteristics
Propagation delay
Setup time
Hold time
Maximum Clock Frequency
Pulse widths and
Power Dissipation
93
Characteristics
Propagation delay time is the interval of the time
required after an input signal has been applied for
the resulting output change to occur
94
Characteristics
Setup time is the minimum interval required for
the logic levels to be maintained constantly on the
inputs prior to the triggering edge of the clock
pulse in order for the levels to be reliably clocked
into the flip flops.
95
Characteristics
Hold time is the minimum interval required
for the logic levels to remain on the inputs
after the triggering edge of the clock pulse in
order for the levels to be reliably clocked into
the flip flop
96
Characteristics
Max. clock frequency is the highest rate at which
a flip flop can be reliably triggered. (specified by
manufacturer)
Pulse widths Minimum pulse widths for reliable

operation are usually specified by the manufacturer
for the clock, preset and clear inputs.
Power Dissipation of any digital circuit is the total
power consumption of the device.
P Vcc I cc
97
Flip Flops Applications
Applications
Parallel date Storage
Frequency Division
Counting
98
Parallel data
storage
99
Frequency division
100
Counting
101
Sequential Circuits
Counters and Shift Registers
102
Counters
Types of Counters
Asynchronous Counters
Synchronous Counters
Up/Down Counters
Cascaded Counters
Counter Applications
103
Counters
Counters
An important application of flip-flops is in the
design digital counters
Types of counters
classified according to the way they are clocked
Asynchronous counters and
Synchronous counters
104
Counters
Asynchronous counters (ripple counters) do
not have a common clock to controls all the flip-flop
stages. The control clock is input to the first stage,
or the LSB stage of the counter. The clock for each
subsequent stage is obtained from the output of
prior stage.
In synchronous counters, the clock input is

connected to all of the flip flops, so that they are
clocked simultaneously
105
Counters
2 bit Asynchronous Counter
106
Asynchronous Counters
3 bit Asynchronous counter
107
3-bit Asynchronous Counter
The counter has three flip-flops and three output
bits, therefore it is a three-stage counter.
The input clock does not trigger both flip-flops,
therefore it is an asynchronous counter
The J and K inputs are tied together and kept HIGH,
so they are considered to be toggle flip-flops
The flip-flops are positive edge triggered.
The count sequence is

000,001,010,011,100,101,110, 111 where the LSB is
Q . Thus it is a MOD-8 binary up counter108
Asynchronous also called ripple
counters
109
Asynchronous counters are commonly referred to
as ripple counters for the following reason
The effect of the input clock pulse is first felt by FF0
This effect cannot get to FF1 immediately due to the
propagation delay through FF0
Then there is the propagation delay through FF1 before
FF2 can be triggered
Thus the effect of an input clock ripples through the
counter, taking sometime, due to propagation delays, to
reach the last flip flop.
This cumulative delay of an asynchronous counter
is a major disadvantage in many applications,
because it limits the rate at which the110
counter can
Glitches
Outputs 000 to 001 delayed

001 to 010 delayed and 000 in between
010 to 011 delayed
011 to 100 delayed and 010 & 000 in between
Output sequence
000 001 000 010 011 010 000 100
i.e, 0 1 0 2 3 2 0 4 instead of 0 1 2 3 4
111
Decoding Glitches
Glitches
If the output of the 3bit asynchronous counter is
given to the input of a 3 to 8 decoder
Y 0
Y 1
Q 0 Y 2
Q 1 Y 3
Q 2 Y 4
Y 5
Y 6
Y 7
i/p sequence - 0 1 0 2 3 2 0 4
112
Decoding Glitches
Glitch Elimination enable the decoded output
at a time after the glitches have had time to
disappear. (ie, in the case of an active HIGH clock,
use the low level of the clock to enable the
decoder)
CTR DIV 10 B C D /D E C 1
0 2
1 3
Q 0 1 2 4
Q 1 4 3 5
Q 2 2 4 6
Q 3 8 5 7
6 9
7 10
8 11
C EN 9
C L K /S T R O B E
113
Asynchronous Decade Counter
Modulus - The maximum number of possible states
of a counter is 2n, where n is the number of flip-flops
in the counter.
Truncated sequence counters with number of
states in their sequence that is less than 2n.
Eg: Decade counter with modulus 10
BCD decade counter - counter with a count
sequence of zero (0000) through nine (1001).
Because its ten state sequence produces the BCD
code. 114
To obtain a truncated sequence it is necessary to
force the counter to recycle before going through all
of its normal states.
For eg., the BCD decade counter must recycle back
to the state 0000 after state 1001.
One method that can be used to achieve recycling
after the count of nine (1001) is to decode ten
(1010) with a NAND gate and connect the output of
the NAND gate to the clear inputs of all the flip-
flops
Fig. shows partial decoding (only Q3 and Q1 are

used for decoding) 115
116
Glitch
Glitch
117
Asynchronous Counter - modulus of
12
Show how a asynchronous counter can be
implemented with a modulus of 12 with a straight
binary sequence from 000 through 1011
Q3 Q2 Q1 Q0
0 0 0 0
- - - - Recycles
- - - -
1 0 1 1
Normal next status
1 1 0 0
118
Asynchronous Counter - modulus of
12
119
Asynchronous Counter
7493A Four bit binary counter
Consists of a single flip flop and a 3 bit
asynchronous counter
It can be used as a divide-by-2 device using
only the single flip flop
Or it can be used as a modulus-8 counter using
only the 3 bit counter portion
Additionally, it can be used as a 4 bit modulus-
16 (counts 0 through 15) counter
This device has two gated reset inputs,
120 R0(1)
7493A - Logic diagram
121
When both the reset inputs are HIGH, the
counter is reset to the 0000 state by active
LOW CLR.
Hence it can be also used as a decade

counter (counts 0 through 9) or as a modulus
-12 counter etc. as the case may be
122
7493A connected as a modulus 16
counter
123
7493A connected as a decade counter
124
7493A connected as a modulus-12
counter
125
The term synchronous as applied to counter
operation means that the counter is clocked
such that each flip flop in the counter is
triggered at the same time
This is accomplished by connecting the clock

line to each stage of the counter
126
A 2-bit Synchronous Counter
127
Timing Diagram
128
Timing details 2 bit synchronous counter
129
130
Timing Diagram
131
State Sequence
CLK Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
132
133
Timing Diagram
134
Synchronous BCD Decade Counter
135
States of a BCD CLK Q3 Q2 Q1 Q0
Decade Counter 0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
136
FFA toggles on each clock pulse, so the logic
equation for its J & K input is
J0 = K 0 = 1
FFB changes on the next clock pulse each time

Q0=1 and Q3=0
J 1 = K 1 = Q 0 Q3
137
FFC changes on the next clock pulse each time
Q0=1 and Q1=1
J2 = K2 = Q0 Q1
FFD changes to the opposite state on the next

clock pulse each time Q0=1, Q1=1 and Q2=1
OR when Q0=1 and Q3=1 (count 9)
J3 = K3 = Q0 Q1 Q2 + Q0 Q3
Eg: 74LS163A 4-bit Synchronous 138
Up/Down Synchronous Counters
An Up/Down counter is one that is capable of
progressing in either direction through a certain
sequence
Also called as bidirectional counter and can have
any specified sequence of state
Most Up/down counters can be reversed at any
point in their sequence
Eg a 3-bit binary up/down counter can have the
following sequence
0,1,2,3,4, 5,4,3,2, 3,4,5,6,7, 6,5 etc
139
Up/Down Synchronous Counters
3-bit up/down sync counter
State transition diagram
(shows the progression
of states through
which the counter
advances when it
is clocked)
140
3-bit Up/Down Sync Counter
Up/down sequence for 3-bit counter
Eg: 74190 Up/Down Decade Counter

141
3-bit Up/Down Sync Counter
142
Cascaded Counters
Counters can be connected in cascade in order to
achieve higher modulus operation.
Cascading means that the last stage output of one
counter drives the input of the next counter
The overall modulus of cascade counters is equal
to the product of each individual modulus
When operating synchronous counters in cascaded
mode it is necessary to use the enable input and
ripple carry output (terminal count) functions
to achieve higher modulus operation
143
Cascaded Counters
Cascaded counter
Two cascaded ripple counters (all J & K inputs are high)

144
Cascaded Counters
Timing diagram
145
Cascaded Counters
A modulus-100 cascade counter using
two decade counters
10KHz 1KHz
100KHz
146
Cascaded Counters
Counter 1 TC goes high when it reaches its last
Only then counter2 is enabled as the TC of

counter1 is connected to ENABLE input of
counter2
Counter1 must go through the entire ten cycle

before counter2 is enabled once
Thus counter2 will reach TC after 100 clock

pulses
Cascaded Counters
When viewed as a frequency divider, the
previous configuration divides the input clock
frequency by 100
Cascaded counters are often used to divide a

high frequency clock signal to obtain highly
accurate pulse frequencies.
Cascaded counter configuration used for such

purposes are called count down chains
148
Counters - Application
Parallel to serial data conversion
(multiplexing)
149
Shift Registers
Shift register functions
Types
Applications
150
Shift Registers
A register that is capable of shifting data one
bit at a time is called a shift register.
The logical configuration of a serial shift
register consists of a chain of flip-flops
connected in cascade, with the output of one
flip-flop being connected to the input of its
neighbour.
The operation of the shift register is
synchronous; thus each flip-flop is connected
to a common clock.
Using D flip-flops forms the simplest type of
shift-registers. 151
Shift Registers - Functions
Functions
152
153
154
Shift Registers - Types
4 bit serial-in/serial-out shift register
155
Waveform (transmitting data 0001)
1 0 0 0
156
After CLK4, all the four bits are entered into the shift
register
To get the data out of the register, they must be
shifted out and taken off the Q3 output
After CLK4, the LSB is available at Q3

On applying CLK5, second bit appears at Q3
CLK6 shifts the third bit to output and so on
While the original four bits are being shifted out, a

new four bit number can be shifted in
157
Serial-in/parallel-
out
158
Waveform
159
Parallel-in/serial-out
160
Parallel-in/parallel-out
161
Bidirectional
162
Shift Registers Applications
Time delay
Serial to parallel data converter
UART
Keyboard encoder
163
Shift Registers Applications
Time Delay
164

Slide 5 - Introduction To Digitial Circuits

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Slide 5 - Introduction To Digitial Circuits

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Introduction to Digital

NOR can function as either a NOR or a negative

NAND & NOR are very popular logic elements

NAND used as AND Gate

NAND used as NOR Gate

NOR used as OR Gate

NOR used as NAND Gate

Combinational Circuits &

Sequential Circuits: Circuits whose outputs

Decoders & Encoders

In its general form, a decoder has n input lines to

For example, if we wish to detect that 1101 occurs on

Accordingly, a 4-input AND / NAND gate and an

Decoder circuit for X=1101 with active HIGH output

Decoder circuit for X=1101 with active LOW output

three bits, eight (23=8) decoding logic gates are

decoder because they are 3 inputs and 8 outputs.

Logic symbol for

The BCD-to-decimal decoder converts each BCD

It is frequently referred to as 4-line-to 10-line

Common Cathode Leds

An encoder accepts an active level (i.e. 1 or 0) on

The logic symbol for Decimal to BCD Encoder

The ten decimal digits on the keyboard must be

When one of the keys is pressed, the decimal digit is

The basic multiplexer has several data input lines

It also has data select inputs that permits digital

Data Select Inputs Input Selected

Interfacing different inputs to a single

The seven-segment display

Multiplexer ADC Microcontroller

For eg: 74151A (8 input mux.) can be used to

Four 3-input AND gates

That is, it functions as an electronic switch (data

Can be also used in demultiplexing

In demultiplexing application the input

One of the enable input is used as the data

Latches and Flip Flops

In most cases, the inputs are sequenced by

With feedback, the state of the circuit becomes

S-R latch (Set-Reset Latch)

Active HIGH Active LOW

Active HIGH Active LOW

When Q output is HIGH, the latch is in SET state and

The 7475 Four bit latches

Each EN is shared by two latches

Difference b/w latch and flip-flops is the method

(a) rising edge triggered (b) falling edge

(a) rising edge triggered (b) falling edge

The operation and truth table for a negative edge

0 0 Rising Hold (no

The term pulse-triggered means that data are

Pulse widths Minimum pulse widths for reliable

Counters and Shift Registers

In synchronous counters, the clock input is

The count sequence is

Outputs 000 to 001 delayed

Fig. shows partial decoding (only Q3 and Q1 are

Hence it can be also used as a decade

This is accomplished by connecting the clock

FFB changes on the next clock pulse each time

FFD changes to the opposite state on the next

Eg: 74190 Up/Down Decade Counter