Professional Documents
Culture Documents
Multimicroprocessor systems
As we all know a single processor system has an upper limit of its
processing capability.
Operation performed :
They are Unable to fetch the code from the memory so they
work under the control of main processor .
How it works :
Control Unit :
Function :
o It interface the coprocessor to the
microprocessor system data bus.
o Monitors the instruction stream.
o If the instruction is an ESCape (coprocessor)
instruction, the coprocessor executes it; if not
the microprocessor executes it.
o It receives , decodes instructions, read and
write memory operands and executes the 8087
PREPARED BY:: S.KAVITHA - AP/CSE ,
8 instruction.
E.PADMA - AP/CSE
Numeric Execution Unit (NEU)
Functions :
Execute all the numeric processor instructions.
It has 8 register (80 bit) stack that holds the operands for
arithmetic instructions & the result.
Programmable shifter :
4) ES error summary
Bit is set if any unmasked error bit (PE,UE,OE, ZE,
DE or IE) is set.
5) PE precision error
PREPARED BY:: S.KAVITHA - AP/CSE ,
12 -Indicate
E.PADMA AP/CSE the result or operand exceed the selected
6) UE Underflow Error
Indicates a non zero result that is too small to
represent with the current precision selected.
7) OE Overflow Error
Indicates a result is too large to be represented.
8) ZE Zero Error
Indicates the divisor was zero while the dividend is
a non-infinity or non zero number.
9) DE Denormalized error
Indicates that at least one of the operands is
denormalized.
1) IC Infinity Control
Selects either affine ( allows positive and negative
infinity) or projective (assumes infinity is unsigned)
2) RC Rounding Control
PREPAREDBY::11 - chop
S.KAVITHA or truncate
- AP/CSE , toward Zero.
15 E.PADMA - AP/CSE
3) PC Precision Control
Sets the precision of the result.
00 -> Single precision (short)
01 -> Reserved
10 -> Double precision (long)
11 -> Extended precision (temporary)
4) Exception Masks
Determine whether the error indicated by the
exception affects the error bit in the status flag.
5) Zero Divide
If any non zero finite operand is divided by zero,
this exception is generated.
6) Denormalized Operand
Exception is generated if at least one of the
PREPAREDoperand or -the
BY:: S.KAVITHA result
AP/CSE , is denormalized.
16 E.PADMA - AP/CSE
Signal Description of 8087
2) A19/S6 A16/S3 :
These are time multiplexed address/ status lines.
These function in a similar way to the
corresponding pins of 8086.
S6 ,S4 & S3 are permanently high, while the S5 is
permanently low.
3) BHE / S7 :
During t1 the BHE / S7 pin is used to enable data on
to the higher byte of the 8086 data bus.
During
PREPARED T2 ,T-3AP/CSE
BY:: S.KAVITHA , Tw and
, T4 this is a status line S7.
19 E.PADMA - AP/CSE
4) Qs1 , Qs0 :
6) BUSY
7) READY
9) CLK
It provide the basic timing for the processor
operation.
10) VCC
A +5V supply
22
11)PREPARED
GND BY:: S.KAVITHA - AP/CSE ,
E.PADMA - AP/CSE
A return line for the power supply.
12) S2 ,S1 and S0
These can be either be 8087 driven (output) or
externally driven (input) by the CPU
s2 S1 S0 Queue status
0 X X unused
1 0 0 Unused
1 0 1 Memory read
1 1 0 Memory write
1 1 1 passive
The 8087 waits for the grant pulse from the host.
The clock pin of 8087 may be connected with the CPU 8086/
8088 clock input.
The pins AD0 AD15 , RESET , A19 /S6 - A16 /S3 , BHE / S7 are
connected to the corresponding pin of 8086/8088.
FPATAN :
Instruction calculates the inverse tangent
The result is stored on the top of the stack.
The content of ST and ST(1) should follow the inequality.
0<=ST(1) < ST< infinity
F2XMI :
Instruction calculates the expression (2x - 1)
Value of x is stored at the top of the stack.
Result is stored back at the top of the stack.
FLY2XP1
It calculate ST(1) * log2[ (ST)+1 ]
Result is stored back on the stack top.
|ST| must lie between 0 and (1- 21/2 /2).
Value of ST(1) must lie between infinity and + infinity
Comparison C3 C0
Stack Top > Source
0 0
Stack Top < Source
0 1
Stack Top = Source
1 0
Not Comparable
1 1
PREPARED BY:: S.KAVITHA -
38
AP/CSE , E.PADMA - AP/CSE
1. FCOM
The content of the top of stack is compared either
with the content of a memory location or with the
content of another stack register.
2. FIST
Instruction test if the content of the stack top is
Zero.
1. FLDZ
Load +0.0 to stack top
2. FLDPI
Load pi(3.14) o stack top
3. FLDLG2
Load the constant Log10 2 to the stack pointer.