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DMA is for high-speed data transfer from/to mass storage peripherals, e.g.
harddisk
drive, magnetic tape, CD-ROM, and sometimes video controllers.
For example, a hard disk may boasts a transfer rate of 5 M bytes per second, i.e.
1 byte transmission every 200 ns. To make such data transfer via the CPU is
both undesirable and unnecessary.
The basic idea of DMA is to transfer blocks of data directly between memory and
peripherals. The data dont go through the microprocessor but the data bus is
occupied.
Normal transfer of one data byte takes up to 29 clock cycles. The DMA transfer
requires only 5 clock cycles.
Nowadays, DMA can transfer data as fast as 60 M byte per second. The transfer
rate is limited by the speed of memory and peripheral devices.
Basic process of DMA
Magistrala de adrese MA
UCP
Magistrala de date MD
Magistrala de comenzi MC
OE# 8 BIT
STB LATCH
A0-A15 BUSEN
AEN A0-A3 A4-A7 CS/ ADSTB
HOLD HRQ
DB0-DB7
HOLDA HLDA I8237A
DREQ0-3
DACK0-3
CPU CLK RESETMEMR# MEMW# IOR# IOW#
CLOCK
RESET
MEMR#
MEMW#
IOR#
IOW# Control buss
D0-D7
Sistem data buss
D0-D7
SelLBUS 12 13 14 15 16 17 18 19
9
BIOW# OE# B7 B0
I8286
BIOR# 11 DIR
A7 A0
SP#/EN# 8 7 6 5 4 3 2 1
LDAT0-7
3 CK 2
4
D0 Q0
5
7 6
8 74LS 9 ADR8-ADR15
13 373 12
14 15
17 16
18 D7 OE# Q7 19
8 D0 Q0 12
7 74LS
13 ADR16-ADR19
6 170 14
5 D3 Q3 15
ADR0 3 WA RA 17
ADR1 2 WB RB 18
BIOW#
1 WE# RE# 19
CSPAGE#
CLK MASTER# AEN1#
CS1#
11 12
XA0 32
A0 CS# CLK
33 36
34 EOP#
35 9 OE#
XA1-XA7 37 AEN 8 C
38 ADSTB
39 74LS573
40 A7 I8237A XA8-XA15
30
29
DB0
28
27
XD0-XD7 26 19
DRQ0 18
23
DRQ1 DRQ0-3
22 17
DB7 DRQ2 16
21
DRQ3
3
4 MEMR# DACK0
25
1 MEMW# 24 DACK0-3
IOR# DACK1 14
2 DACK2
IOW# DACK3
15
6
13
READY
RESET
HRQ HLDA T/C
10 7
CLK
CS2#
32
A0 CS# CLK
33
EOP#
AEN OE#
ADSTB C
DRQ0
DRQ1 DRQ5-7
DB7 DRQ2
DRQ3
MEMR#
MEMW# DACK0
DACK1 DACK5-7
IOR#
IOW# DACK2
DACK3
READY
RESET
HRQ HLDA
HRQ
HLDA