VHDL

Counters and Memories

Multi- Flip Flops

Either latches or flip-flops can be interconnected
to form memory structures that store multiple bits
of information as a unit
Flip-flops can also be combined to form shift
registers, shift register counters, and counters
These simple sequential systems find widespread
use as components in more complex systems

Shift Register Digital Noise Filter

The purpose of this filter is to reject short-duration noise
spikes at its data input cx
The filters output y can change only after its input has had
the same value at three consecutive triggering clock edges

Shift Register Digital Noise Filter

The first flip-flop of the shift register is used to reduce the chances of a
meta-stable event if the input data is asynchronous
The filtered output is computed from the rightmost 3 bits of the shift register
If all three of these bits are zeros "000", then output y is assigned a '0
If all three of these bits are ones "111", then y is assigned a '1
For any other combination of these 3 bits, y remains unchanged
The filter operation is accomplished by the innermost if
statement. The shift operation is accomplished by the
assignment statement for q that uses a concatenation
operation.

SHIFT REGISTERS COUNTERS

Using feedback, a shift register can be configured to
produce a characteristic sequence of states
Such a shift register functions like a counter with a
characteristic count sequence and is often called a shift
register counter
Two examples of shift register counters implemented by
connecting their serial outputs back to their serial
inputs- Johnson Counter and Ring Counter

OPERATORS
LOGIC OPERATORS:
(AND ,OR, NOT, NAND, NOR,
XOR, XNOR )
Relational Operators:
= equal to
/= not equal to
< less than
<= less then or equal to
> greater than
>= greater than or equal to
Adding Operators
+ addition
subtraction
& concatenation

Multiplying Operators
*Multiplication
/ division
mod modulus
rem remainder
Misc. Operators
** exponentiation
left operand = integer or
floating point
right operand = integer
only
abs absolute value
not inversion

Johnson Counter
A Johnson counter simply connects the complement of its serial
output back to its serial input
If a Johnson counter is cleared when reset, its serial output is 0.
Since the complement of its serial output appears at its serial input,
at each subsequent triggering clock edge a 1 is shifted in, until the
counter is filled with 1s
With its serial output now a 1, a 0 is shifted in at each subsequent
triggering clock edge, until the counter is filled with 0s, making its
serial output a 0
From this point, the count sequence repeats

Johnson Counter
The number of unique states a counter has is its modulus
The count (or state sequence) for a Johnson counter is 2 n counts
long (modulus 2 n), where n is the number of stages in the shift
register

RING COUNTER
A ring counter feeds its serial output directly back to its serial input
If at reset the shift register is loaded with a single 1, this 1 is
shifted around the register over and over. The length of the count
sequence is simply n

COUNTERS
counters are used to count events, generate time
intervals, generate events, and divide down an input
signal to create a lower frequency output signal
A counters next state is the state it goes to from its
present state at a triggering clock edge
A simple counter transitions from one unique state to
another, until it eventually returns to its initial state, after
which its state transitions repeat.

COUNTERS
The state transitions of a counter are clearly depicted by a state
diagram
A state diagram for a 3-bit binary up counter is given in Fig
The counter is initialized to 000 at reset and counts up to 111 before
recycling to 000.
A 3-bit binary counter has a modulus of 8, or is, equivalently, a
modulo-8 counter

COUNTERS
Two ways to solve this problem are:
1. Use type integer signals or variables along with the
predefined + and operators, then use functions to
convert the integer results to std_logic
2. Use type unsigned from the package NUMERIC_STD,
which also overloads the + and operators for this type,
then convert the unsigned results to std_logic_vector

Frequency Divider
A truncated sequence counter counts through a sequence that is not a power of 2
If at a triggering clock edge the present count is the last count desired in the sequence,
the counter is loaded with the starting (initial) count value, instead of being
incremented to the next binary count
The counter counts the input load value (divisor) down by one at
each triggering clock edge
When the present count is "0010" at a triggering clock edge, the
count goes to "0001" and simultaneously output q becomes '1
When the present state is "0001", the counter loads the value of
divisor at the next triggering clock edge and simultaneously q
becomes '0'.

BCD Counters
It counts in decimal, a two-digit BCD counter counts from 00 decimal to 99 decimal. On the
next count, it rolls over to 00 decimal
The least significant four bits of the counter represent the least significant decimal digit (0
to 9) encoded in BCD
The most significant four bits represent the most significant decimal digit, encoded in BCD
Since a BCD digit ranges from 0000 to 1001 in binary, when the counters value is
00001001 (09 decimal), its value on the next count must change to 00010000 (10 decimal).

Detecting the Non-clock Edge Signals

If a design requires that some action be carried out when an event occurs on a signal
other than the clock signal
Prior to IEEE Std 1076.6-2004, only one signal was allowed to be used as the clock
in a process
As a result, a non-clock signal could not simply be treated like a second clock signal
so that its edge could be detected
IEEE Std 1076.6-2004 now allows multiple clock signals in a process, as long as the
occurrence of the clock edges is mutually exclusive

MICROPROCESSOR COMPATIBLE PULSE WIDTH

MODULATED SIGNAL GENERATOR
A pulse width modulated (PWM) signal has a fixed period, but its duty cycle
can be changed
There are many applications for PWM signals in electronic systems. A
common one is to control the speed of a DC motor. The PWM signal may be
used to drive the gate of a HEXFET transistor that turns the motor ON when
the signal is 1 and OFF when it is 0
If the period of the PWM signal is sufficiently short, the motors speed is
proportional to the signals duty cycle. If the period of the PWM signal is too
large, the motors speed is no longer controlled by the average value of the
PWM signal
Instead, the motor runs full speed when the PWM signal is a 1 and will,
eventually, stop when it is a 0.

PWM signal Generator

A microprocessor compatible PWM signal generator (PWMSG)
design based on counter and register functions is to be designed
The PWMSG is designed to be interfaced to the bus of a
microprocessor. The microprocessor writes a data byte to the
PWMSG to specify the duty cycle
The PWMSG then generates an output signal with the specified
duty cycle. The output signals duty cycle remains constant
until the microprocessor writes a new data byte to the PWMSG.

BLOCK DIAGRAM

PWM signal Generator

The microprocessors clock, clk, is used to drive
the clock input of the PWMSG
A pre-scalar divides down the microprocessor
clock to create a lower frequency signal, ps
This lower frequency signal is used as the
enable to the period counter, which, when
enabled, counts at the triggering edge of the
microprocessor clock

PWM signal Generator

The 8-bit period counter sets the period of the
PWM signal to be equal to 256 times the period
of the prescalar output ps
The period counters output period_cnt is an 8bit value that continuously cycles from 0 to 255
in binary
The time it takes period_cnt to cycle from 0
through 255 and then roll over to 0 determines
one period of the PWM output signal pwm_out.

PWM signal Generator

The duty cycle subsystem contains an 8-bit register, duty_cycle. This register is
written by the microprocessor to control the duty cycle
The microprocessors data bus provides the data to be written at the data input of
the duty cycle subsystem and controls the write operation using the cs_bar and
we_bar inputs
The duty cycle of pwm_out is equal to the value written to the duty_cycle
subsystem divided by 256
For example, to obtain a 25% duty cycle the microprocessor must write the value
64 to the duty_cycle register
The comparator compares the 8-bit value period_cnt from the period counter with
the 8-bit contents of register duty_cycle. If period_cnt is less than duty_cycle, then
pwm_out is a '1'; otherwise, it is a '0'

MEMORIES
We consider memories that consist of multiple multi-bit
latches or multiple registers
Such a memory is a single storage unit that consists of a
two-dimensional array of memory elements
This two-dimensional array of bits is equivalent to a onedimensional array of multi-bit latches or registers
To be uniquely identified, each multi-bit latch or register
has an address.

MEMORIES
The external organization of a memory is expressed as the
number of words the number of bits per word in the
memory. This is also referred to as the length width, or
depth width, or aspect ratio of the memory
It is typically written as 2m n, where m is the number of
address inputs used to select a single word from the array of
words and n is the number of data bits in each word
For example, a 16 8 memory contains 16 words each 8 bits
wide. It has 4 address bits (inputs).

MEMORIES
RAM stands for random access memory. A random access memory is
one in which the amount of time it takes to read (access) a word from
any one address (location in the memory) is essentially the same as for
reading from any other address in the memory
This is in contrast to what is the case for a serial memory. However, the
term RAM is commonly used to mean a memory that can be written and
read during its normal operation
This is in contrast to read-only memory (ROM), which although
random access, can only be read during its normal operation. A ROMs
contents are defined only once; therefore, a ROM stores constant values

MEMORIES