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PLL implementation
PHASE DETECTOR
Loop filter
VCO
If the loop is locked, the input and output frequencies are equal, the
PD generates repetitive pulses,
The loop filter extracts the average level, and the VCO senses this
level so as to operate at the required frequency.
: the PD input is a phase quantity, the PD output and the LPF output
are
voltage quantities, and the VCO output is a phase quantity.
Fequency multiplication
The M circuit is a counter that generates one output pulse
for every M input pulses .
in the locked condition, F = in and hence out = Min.
The divide ratio, M, is also called the modulus
PFD
Phase/Frequency detector
The circuit produces two outputs, QA and QB, and operates based on
the following principles:
(1) a rising edge on A yields a rising edge on QA (if QA is low),
and (2) a rising edge on B resets QA (if QA is high).
if A > B, then QA produces pulses while QB remains at zero.
Conversely, if B > A, then positive pulses appear at QB and QA =
0.
On the other hand, if A = B, the circuit generates pulses at either
QA or QB with a width equal to the phase difference between A and B.
Thus, the average value of QA QB represents the frequency or
phase difference.
Design of pfd
If the PFD is in state 0, then a transition on A takes it to
state I, where QA = 1, QB = 0. The circuit remains in
this state until a transition occurs on B,upon which the
PFD returns to state 0.
PLL-Based Modulation
In addition to frequency synthesis, PLLs can also
perform modulation.
transmitter architectures that merge the modulation
and frequency synthesis functions
FSK and GMSK modulation can be realized by means of
a VCO that senses the binary data
Open loop modulation
In loop modulation
such a system first disables the baseband data path and
enables the PLL, allowing fout to settle to NfREF. Next,
the PLL is disabled and xBB(t) is applied to the VCO.
Divider Design
integer-N synthesizers produce an output frequency that
is an integer multiple of the reference frequency
If N increases by 1, then fout increases by fREF; i.e., the
minimum channel spacing is equal to the reference
frequency
The divide ratio must be programmable from, say, N1 to
N2 so that N1fREF = f1 and N2fREF = f2