PIC Microcontroller

Introduction
Peripheral Interface Controllers (PIC)
is one of the advanced
microcontrollers developed by
microchip technologies.
They are advanced than 8051.
PIC microcontroller family uses
modified Harvard architecture.
program memory bus and a data
memory bus to access two separate
memories.

Block Diagram

CPU
The CPU in PIC normally supports Reduced
Instruction Set Computer (RISC) architecture.
CPU consists of several sub-units such as
instruction decoder, ALU, accumulator, control
unit, etc.
RISC structure gives the following advantages.
The RISC structure only has 35 simple instructions
as compared to others
The execution time is same for most of the
instructions (except very few numbers).
The execution time required is very less (5 million
instructions/second (approximately)

Memory
Memory partitioned into data memory and
program memory
Each of them have separate bus.
Based on type, PIC chip also has certain amount
of RAM, ROM, EEPROM, other flash memory.
RAM memory is a complex memory module in a
PIC chip.
RAM memory associated with special function
registers, general purpose registers and
memory BANK modules

Registers
Information is stored in CPU at memory
locations called a register.
Register file is used to denote locations that
an instruction can access via address
Registers can be thought of as the CPUs
tiny scratchpad (8 bit locations)
General Purpose Register (GPR)
Used to store data and addresses

Special Function registers (SFR)

To configure different peripherals

PIC16F877A

High performance RISC CPU

Only 35 single-word instructions
Operating speed: max 20 MHz clock input
8K x 14 words of Flash Program Memory,
368 x 8 bytes of Data Memory (RAM),
256 x 8 bytes of EEPROM Data Memory
All single-cycle instructions except for
program branches, which are two-cycle
33 I/O pins

Pin Diagram

Pin Configuration

Block
Diagram

Memory Organization
Program memory
Data Memory
Each memory has separate buses so
that concurrent access can occur.

Program Memory
Organization
PIC16F87XA devices have a 13-bit
program counter
The PIC16F877A has 8K words x 14
bits of Flash program memory
The Reset vector is at 0000h and the
interrupt vector is at 0004h.

PIC16F877A
PROGRAM
MEMORY MAP
AND STACK

Data Memory Organization

Data memory is partitioned into
multiple banks
It contains the General Purpose
Registers and the Special Function
Registers
Bits RP1 (Status<6>) and RP0
(Status<5>) are the bank select bits.

 Each bank extends up to 7Fh (128

bytes).
The lower locations of each bank are
reserved for the Special Function
Registers.
Few frequently used Special Function
Registers from one bank may be
mirrored in another bank

Register
File Map

GENERAL PURPOSE REGISTER

FILE
It can be accessed either directly, or
indirectly, through the File Select
Register (FSR).

SPECIAL FUNCTION
REGISTERS
These registers are used to configure
the operation of the CPU and its
peripherals
These registers are implemented as
static RAM

RAM addressing
Two types of addressing modes
direct addressing
address forms part of the instruction

indirect addressing
Address is taken from the File Select
Register (FSR)

Status Register
It contains arithmetic status of ALU,
reset status and bank select bits for
data memory
Status register can be the destination
for any instruction

The Status register

 Write

to Z, DC, C bits is disabled.

andbits are not writable
Eg, CLRF STATUS, will clear the upper
three bits and set the Z bit. So the
Status register will be 000u u1uu
(where u = unchanged).
BCF, BSF, SWAPF and MOVWF
instructions are used to alter status
register

OPTION_REG Register
It is a readable and writable register
It contains various control bits to
configure
TMR0 prescaler/WDT scaler
the external INT interrupt,
TMR0 operation
weak pull-ups on PORTB.

PCL and PCLATH

Program Counter (PC) is 13 bits wide
Lower 8 bits of PC comes from PCL
register
PCL register is readable and writable.
Upper bits (PC<12:8>) are not readable
But are indirectly writable through the
PCLATH register
On Reset, the bits of the PC will be
cleared.

Loading of PC

COMPUTED GOTO
It involves adding an offset to the
program counter (ADDWF PCL).
Care to be exercised to check if
result crosses a PCL memory
boundary
CALL AND GOTO INSTRUCTIONS
They provide 11 bits of addressing
Two Most significant bits taken from
PCLATH register 4th & 3rd bit to form
13 bit PC value.

CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
SUB1_P1
ORG 0x500
: ;called subroutine
BCF PCLATH,4
;page 1 (800h-FFFh)
BSF PCLATH,3 ;Select page 1
:
;(800h-FFFh)
RETURN ;return to
CALL SUB1_P1 ;Call subroutine
;Call subroutine
in
;in page 0
:
;page 1
;(000h-7FFh)
(800h-FFFh)
:
ORG 0x900
;page 1 (800hFFFh)

STACK TRANSFER
PIC16F877A has an 8-level deep x 13-bit wide
hardware stack
13-bit value is transferred between Stack and
Program Counter
stack space is not part of either program or data
space
Stack pointer is not readable or writable
PC is PUSHed onto the stack when a CALL
instruction is executed, or an interrupt causes a
branch.
Stack is POPed in the event of a RETURN, RETLW
or a RETFIE instruction
Stack operates as a circular buffer
PCLATH register contents are unchanged after a
RETURN or RETFIE instruction is executed

Addressing Modes
Two types of addressing modes for
accessing data memory
Direct addressing mode
Indirect addressing mode

Direct addressing
Direct Addressing is done through a
9-bit address for the RAM.
Address obtained concatenating 7
bits of direct address of an
instruction with two bits (RP1, RP0)
from STATUS register
bsf STATUS, RP0 ;Bank 1
movlw 0xFF ;w=0xFF
movwf TRISA ;address of TRISA register is
taken from
;instruction movwf

Direct addressing mode

Indirect Addressing
Indirect addressing does not take an address
from an instruction
Address derived from IRP bit of STATUS and
FSR registers
Addressed location is accessed via INDF
register
INDF register holds the address indicated by a
FSR. Eg.
movlw 0x0C
movwf FSR
movwf INDF

Indirect Addressing

Instruction Set

General Format for

Instructions

Destination in Byte Oriented

Instruction

Special Function Registers as

Source/Destination
STATUS Register as Destination
Z, C, DC and OV bits may be set or
cleared as a result of the instruction
It will overwrite the original data bits
written
Eg. CLRF STATUS; clear STATUS register
It will set the Z bit leaving 0000 0100b
as result

PCL as Source or
Destination
Read PC: PCL -> dest; PCLATH does
not change;
Write PCL: PCLATH -> PCH;
8-bit destination value -> PCL
Read-Modify-Write: PCL -> ALU
operand
PCLATH -> PCH;
8-bit result -> PCL

Bit Manipulation
All bit manipulation instructions
follow read-modify-write (R-M-W)
operation on the specified register
It will first read the entire register,
operate on the selected bit and then
write the result back

Q Cycle Activity
Each instruction cycle (Tcy) is comprised of four Q
cycles (Q1-Q4)
The Q cycle is the same as the device oscillator
cycle (TOSC).
The Q cycles provide the timing/designation for the
Decode, Read, Process Data, Write etc., of each
instruction cycle.
The four Q cycles can be generalized as
Q1:
Q2:
Q3:
Q4:

Instruction Decode Cycle or forced No Operation

Instruction Read Cycle or No Operation
Process the Data
Instruction Write Cycle or No Operation

Q Cycle Activity

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