FACULTY DEVELOPMENT PROGRAMME

EC 6601 - VLSI DESIGN

SEQUENTIAL LOGIC CIRCUITS
Dr A N JAYANTHI
Associate Professor/ECE
SRI RAMAKRISHNA INSTITUTE OF TECHNOLOGY
COIMBATORE-641010
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OVERVIEW

Introduction to Sequential circuits

Sequential circuit types
Memory Cell
D Latch
CMOS Positive Level Sensitive Latch
Flip Flops
CMOS Positive Edge Triggered D Flip Flop
Registers
CMOS SR Latch using NOR gate version
CMOS SR Latch: NAND Gate Version
Clocked SR Latch NOR version
Clocked CMOS SR Latch - AOI Implementation
Clocked CMOS JK Latch: NAND Version
Clocked CMOS Logic (C2MOS)
Clocking Strategies for Finite State Machine & Pipelined Systems
Timing a Pipelined System
The Effect of Clock Skew on a Pipeline
Clock Synchronization Using Phase Locked Loops
Dynamic Logic
Domino Logic
NORA Logic
Static and Dynamic Memories
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Sequential logic circuits/Regenerative

Circuits

Sequential logic circuits contain one or more combinational logic blocks

along with memory in a feedback loop with the logic
The next state of the machine depends on the present state and the
inputs
The output depends on the present state of the machine and perhaps
also on the inputs
Mealy machine: output depends only on the state of the machine
Moore machine: the output depends on both the present state and
the inputs

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Sequential Circuit Types

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Sequential Circuit Types

Bistable circuits have two stable operating points and will remain
in either state unless perturbed to the opposite state
Memory cells, latches, flip-flops, and registers

Monostable circuits have only one stable operating point, and

even if they are temporarily perturbed to the opposite state, they
will return in time to their stable operating point

Astable circuits have no stable operating point and oscillate

between several states
Ring oscillator

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Memory Cell: Two-Inverter Basic

Bistable Element

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Memory Cell: Two-Inverter Basic

Bistable Element

The memory cell (or latch) has two stable states where the dc voltage
transfer curves cross at the VOH and VOL points, but also exhibits an
unstable state where the VTCs cross near their Vth switching points.

In actual physical circuits the memory cell will never stay at the unstable
point, since any small electrical noise in the circuit will trigger it to one side
or the other

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Memory Cell: Two-Inverter Basic

Bistable Element

The CMOS SRAM will either be in state

0 with V01 at GND and V02 at VDD
or in state 1 with V01 at VDD and
V02 at GND.

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D LATCH / LEVEL SENSITIVE LATCH

D Latch is called so because the state of the o/p depends on the
state of the clock signal.
D latch can be built from 2 i/p Mux + 2 inverters
2 i/p mux can be built from a pair of Transmission gates
OPERATION:
CLK = 1 , The Latch is Transparent
CLK falls to 0, the latch becomes OPAQUE
This is POSITIVE Level Sensitive Latch.
Invert the Control connections to Multiplexer to get
NEGATIVE Level Sensitive Latch.
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CMOS Positive Level Sensitive Latch

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Timing Diagram

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Timing Diagram- tsetupand

thold
In order to guarantee adequate time to get correct data at the first
inverter input before the input switch opens,

the data must be

valid for a given time (tsetup) prior to the CLK going
low.
In order to guarantee adequate time to set the latch with correct data,

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the data must remain valid for a time (thold) after the
CLK goes low.
Violations of Tsetup and Thold can cause metastability problems
and chaotic transient behavior.

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Flip Flops
Combine positive and negative level Sensitive Latches to construct Egde
Triggered Flip Flop.
I Latch= MASTER
II Latch= SLAVE
OPERATION:
1. When CLK is LOW ,Master latch follows D input and Slave Latch holds
previous value.
2. When CLK goes from 0 to 1 ,Master latch is OPAQUE and holds D Value
at the time of the CLK Transition. Slave latch is TRANSPARENT, passing the
stored master value to the output of the SLAVE LATCH. Output is
unaffected from D because master is disconnected from D
3. When CLK goes from 1 to 0 , the SLAVE Latch holds its Value and the
MASTER starts SAMPLING the input again.
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CMOS Positive Edge Triggered

D Flip Flop

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CMOS Positive Edge Triggered D

FlipFlop

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D Flip flop

The Flip flop copies D to Q on the rising edge of the Clock. Thus Positive
edge triggered flip flop/D Flip flop/D register/Master Slave Flip flop.
Reverse the latch polarities to get negative edge triggered flip flop.

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Register

Collection of D Flip flops sharing a common clock input

Register is a flip flop with multi bit D and Q busses.

CLOCK SKEW is a problem that occurs due to variation in the clock

arrival time..i.e., one flip flop triggers earlier and the other triggers late. If
skew is high , it results in HOLD TIME failures.
To avoid Hold time problems:
1.Two phase Non overlapping Clocks
2.As long as the phases of the clocks dont overlap, hold time failures will not
occur.(Atleast one latch will be transparent)

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SR Latch-NOR Gate Version

The NOR-based SR Latch contains the basic memory cell

(back-to-back inverters) built into two NOR gates to allow
setting the state of the latch.

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SR Latch-NOR Gate Version

SR Latch Logic Diagram

Truth Table

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CMOS SR Latch: NAND Gate Version

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CMOS SR Latch: NAND Gate Version

SR Latch Logic Diagram

Truth Table

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Clocked SR Latch: NOR

Version

Clocked SR Latch Logic Diagram

Timing Diagram

The latch is responsive to inputs S and R only when CLK is

high
When CLK is low, the latch retains its current state
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Clocked CMOS SR Latch

- AOI Implementation

Clocked SR Latch Logic using AOI

Diagram

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Circuit
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Clocked CMOS SR Latch

- AOI Implementation
Only 12 transistors required
When CLK is low, two series legs in N tree are open and
two parallel transistors in P tree are ON, thus retaining
state in the memory cell
When CLK is high, the circuit becomes simply a NORbased CMOS latch which will respond to inputs S and R

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Clocked CMOS JK Latch: NAND

Version

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Clocked CMOS JK Latch: NAND Version

If J = K = 0, the latch will hold its present state

If J = 1 and K = 0, the latch will set on the next positive-going
clock edge, i.e. Q = 1, Q = 0
If J = 0 and K = 1, the latch will reset on the next positive-going
clock edge, i.e. Q = 1 and Q = 0
If J = K = 1, the latch will toggle on the next positive-going
clock edge

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Clocked CMOS JK Latch: NAND Version

To prevent the JK Latch from oscillating continuously during the clock

active time,
the clock width must be kept smaller than the switching delay time of the
latch.
Otherwise, several oscillations may occur before the clock goes low again.
In practice this may be 6difficult to achieve.

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Clocked CMOS Logic (C2MOS)

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Clocked CMOS Logic (C2MOS)

Clocked CMOS logic has been used for very low power CMOS and/or for
minimizing hot electron effect problems in N-FET devices
Clocking transistors allow valid logic output only when clk is high
Clocking transistors may be at output end of logic trees (maximum
performance) or at power supply end of logic trees (maximum protection
from hot electrons)

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Clocking Strategies for Finite State

Machine & Pipelined Systems
VLSI systems make use of storage
elements and states, with clock(s) to
control the sequencing

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State Machine and Pipelined System

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Timing Diagram

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Timing a Pipelined System

Minimum cycle time Tc obtainable given by

T c = T q + T d + Ts
Tq is the clock-to-Q output delay of Register A
Td is the total worst case delay through the combinational logic
Ts is the set-up delay time of Register B

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The Effect of Clock Skew on a

Pipeline

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The Effect of Clock Skew on a

Pipeline

Design of a pipelined machine assumes that clock edges will

appear at each register at a precise time to

If delay occurs in clock distribution due to RC wire delays, LC

ringing on the clock nets, or buffer delay, the pipeline timing will
be skewed.
Can cause a latch or register to be set with incorrect data

Example:
Register M1 is set by the clock at Tc1, providing data inputs to the
combinational logic and then to register M2
Register M2 is supposed to latch in old data at the same clock edge
But, if the delay to

Tc2 > Tc1 + Tq1 + logic

delay, M2 will incorrectly store the new data rather than the
previous data.

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Clock Synchronization Using Phase

Locked Loops

Phase Locked Loop (PLL) is used to synchronize an on-chip

generated clock with a system clock at some point on the chip.
Reduces clock skew to zero at the sensing point

If chip does not contain PLL clock skew will be there.

So use PLL, to avoid Clock Skew.

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Dynamic Logic
It occupies less areacompare to static CMOS
It has higher speed compare to static CMOS
It has less power .compare to static CMOS

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Dynamic Logic

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Dynamic Logic
The precharge and the evaluation
phase.
In what mode the circuit is operating
is determined by the signal , the
clock signal.

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Dynamic Logic

Output for F= (AB + C)I

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Advantages of Dynamic
Logic

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DisAdvantages of Dynamic
Logic

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Domino Logic

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Features of Domino Logic

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NORA Logic-NO RAce Logic

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NORA Logic-NO RAce Logic

A NORA datapath consists of a chain of alternating and
modules. While one class of modules is precharging with its output
latch in hold mode, preserving the previous output value, the other
class is evaluating.
Data is passed in a pipelined fashion from models to module. The
resulting datapath combines high performance with high layout
density.

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Static Memories and Dynamic

Memories

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References

Neil H.E.Weste, Principle of CMOS VLSI Design: A System

Perspective.
Jan M. Rabaey, Digital Integrated Circuits, A Design Perspective
Michael John Sebastian Smith, Application-Specific Integrated Circuits,
Addison Wesley, 1997.

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Thank You

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