Department of Electrical

Engineering

IEEE India Council

Faculty of Engineering & Technology

Jamia Millia Islamia, New Delhi, India

Minimum Multiplier Implementation

of a Comb Filter using Lattice Wave
Digital Filter
Paper Id: 1570186269
BY:
Richa Barsainya, Meenakshi Aggarwal
Tarun Kumar Rawat
(Netaji Subhas Institute of Technology,
New Delhi)

Department of Electrical
Engineering

IEEE India Council

Faculty of Engineering & Technology

Jamia Millia Islamia, New Delhi, India

Highlights

Design

and implement the comb lattice wave digital filter with only one
multiplier

Lattice

wave digital filter is used for filter realization due to its excellent
properties

A design level area optimization is achieved by converting constant multiplier

into shift and add using canonical signed digit code (CSDC) technique.

FPGA implementation of comb lattice wave digital filter is accomplished for

small area and low power dissipation.

Department of Electrical
Engineering

IEEE India Council

Faculty of Engineering & Technology

Jamia Millia Islamia, New Delhi, India

Introduction

A Comb filter is known to have multiple pass-bands and stop-bands.

The comb filter finds applications in the area of control Engineering, communication
engg. and biomedical engg. to remove the power line disturbance

The frequency response of the ideal comb filter is follows

0, k0
H ideal (e j )
1, otherwise

.(1)

Department of Electrical
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IEEE India Council

Faculty of Engineering & Technology

Jamia Millia Islamia, New Delhi, India

Fig. 1 Notch filter configuration using first order all-pass filter

H ( z) F ( z L )

1
1 z L A( z L )
2

Fig. 2 Comb filter design using scaled notch filter

Department of Electrical
Engineering

IEEE India Council

Faculty of Engineering & Technology

Jamia Millia Islamia, New Delhi, India

LATTICE WAVE DIGITAL

FILTER

LWDF is a specific class of wave digital filter.

The LWDFs are visualized as a connection of first- and second-order all-pass sections.
These digital all-pass sections are basically known as adaptors. Every adaptor has a
multiplier coefficient, which controls the response of the all-pass section.

The LWDFs uses four types of adaptors as the filter building blocks.
All four adaptors are equivalent since
b1 they
a1 implement
(1 )a2 the following equations:
b2 (1 )a1 a 2

.(4)

where is the multiplier coefficient of the adaptor. The value of always lies in the
range of -1 to 1.

Table I. Type of Adaptors

Adaptor Type
range
/ conversion
Type I
Type II
Type III
Type IV

1
0
2

1
2

1
2

1
1
2

Fig. 3 Four equivalent structures of two port adaptor

Department of Electrical
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IEEE India Council

Faculty of Engineering & Technology

Jamia Millia Islamia, New Delhi, India

DESIGN EXAMPLE
The comb filter specification using scaled first order notch is chosen as
notch frequency, 0= 0.51
The transfer function of notch filter is obtained as
-1

1
1 0.03141 z

F ( z ) 1 z
-1
2
1

0.03141z

H ( z) F ( z L )

Then refereeing to
.

1
1 z L A( z L )
2

(5)
.(6)

choosing L = 4, the resultant comb filter transfer function is obtained as

-4
1
4 0.03141 z
H ( z ) F ( z ) 1 z
-4
2
1 0.03141z
4

...(7)

Department of Electrical
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Faculty of Engineering & Technology
Jamia Millia Islamia, New Delhi, India

IEEE India Council

The LWDF design of comb filter with minimum multiplier is obtained, where only
one adaptor is required and each adaptor comprises of single multiplier.

Fig. 4 Lattice Wave digital realization of Comb filter

For the all-pass section A1(z), the obtained adaptor coefficient 1 is -0.03141.
The adaptor Type I is required for the allpass section.

Department of Electrical
Engineering
Faculty of Engineering & Technology
Jamia Millia Islamia, New Delhi, India

IEEE India Council

Fig. 5 Magnitude and phase response of designed Comb filter

Department of Electrical
Engineering

IEEE India Council

Faculty of Engineering & Technology

Jamia Millia Islamia, New Delhi, India

FPGA Implementation

The wave digital structures of comb filter are coded in Verilog HDL language and
synthesis, translate, map, place and route of the designs are done using Xilinx ISE
13.4 targeting Spartan3 (XC3s200-ft256) FPGA device.

The structure is tested and simulated on ISim simulator by applying all possible
test vectors.

The performance analysis is carried out in term of hardware utilization, maximum

frequency and power dissipation.

The power dissipation of the proposed filter structure is estimated by Xilinx

Xpower tool. The hardware implementation is illustrated by a design example.

Department of Electrical
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Faculty of Engineering & Technology
Jamia Millia Islamia, New Delhi, India

IEEE India Council

To reduce the hardware cost as well as to increase the speed, the coefficients of the
filter are represented in canonic signed digit (CSD).

The nonzero bits in a CSD number are approximately reduced to wd/3 while a twoscomplement number has an average wd/2 nonzero bits, where wd is the coefficient
wordlength .

The resulting digital filter can be easily implemented using shifts and add multipliers.

Department of Electrical
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IEEE India Council

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Jamia Millia Islamia, New Delhi, India

The proposed structure of LWD fixed coefficient Comb filter is implemented using
the CSD technique with CSAs.

LWD filter structures use first-order allpass sections as their building blocks and
are composed of adders/subtractors, multipliers and delay elements (D-Flip flops)
as shown in Fig. 6.

The multipliers are replaced with shifters and adders. Wave digital allpass sections
shown in Figs. 6 is mapped to CSAs and shown in Fig. 7.

Fig. 6 First-Order allpass section

Department of Electrical
Engineering
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Jamia Millia Islamia, New Delhi, India

Fig. 7 Carry-save mapping of first-order Richards allpass

section

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Department of Electrical
Engineering

IEEE India Council

Faculty of Engineering & Technology

Jamia Millia Islamia, New Delhi, India

Results and Analysis

Table II. Coefficients for the comb filter using scaled first-order all-pass sections

Coefficients

Range

Adaptor
Type

Coefficient

1 =0.03141

-0.03141

CSD
Equivelent
0.0000100

Table III. Hardware utilization summary of the comb filter

4 input LUTs
Slices
Slices flip-flops

Type

Used Available
Comb filter
using
Richardsscaled
first- order
section

44

Utilization

3840

1%

used
39

Available Utilization used Available Utilization

1920

2%

37

3840

1%

Table IV. Minimum period Tmin , maximum sampling frequency fmax and total power
dissipation for the scaled first-order comb filter
Type

Tmin (ns)

fmax (MHz)

Richards Scaled Comb filter

3.398

294.291

Power Dissipation (mW)

50.79

Department of Electrical
Engineering

IEEE India Council

Faculty of Engineering & Technology

Jamia Millia Islamia, New Delhi, India

Conclusion

The design of minimum multiplier comb filter using lattice wave digital structure is
obtained.

Due to the properties of LWDF the proposed comb filter is stable, less sensitive to
quantization and has low roundoff noise.

The example shows that this filter design utilizes only one multiplier and is realized
using LWDF structure.

To reduce the hardware cost filter coefficients are implemented using their CSD
equivalent.

The proposed design of comb filter is implementation on FPGA using Richards firstorder section.

Speed is improved by mapping Richards sections to carry save adders rather than
ripple carry adders.

Department of Electrical
Engineering

IEEE India Council

Faculty of Engineering & Technology

Jamia Millia Islamia, New Delhi, India

References
[1] A. Nehorai and B. Porat, Adaptive comb filtering for harmonic signal enhancement, IEEE Trans. Acoust.,

Speech, Signal Processing, vol. ASSP-24, pp. 1124-1138, Nov. 1986.

[2] J. A. Van Alste and T. S. Schilder, Removal of based-line wander and power-line interference from the ECG
by an efficient FIR filter with reduced number of taps, IEEE Trans. Biomed. Eng., vol. BME-32, pp. 1052-1060,
Dec. 1985.
[3] Y. K. Jang and J. F. Chicharo, Adaptive IIR comb filter for harmonic signal cancellation, Int. J. Electron., vol.
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[4] S. K. Mitra, Digital signal processing, Mc Graw Hill, 4th edition, 2013.
[5] T. K. Rawat, Digital signal processing, Oxford publication, 1st edition, 2015.
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[9] S. C. Dutta Roy, Balbir Kumar and Shail Bala Jain, FIR notch filter design-A review, Electronics and
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Department of Electrical
Engineering

IEEE India Council

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Jamia Millia Islamia, New Delhi, India

References Contd.
[10] Y. V Joshi and S. C. Dutta Roy, Design of IIR digital notch filters, circuits systems signal processing, vol.
16, no. 4, pp. 415-427, 1997.
[11] A. Fettweis, Digital filter structures related to classical filter networks, Arch. Elektron. and
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[12] A. Fettweis,Wave digital filters: Theory and practice, IEEE Proc., vol. 74, no. 2, pp. 270-327, 1986.
[13] R. Barsainya, T. K. Rawat, R. Mahendra, A new realization of wave digital filters using GIC and fractional
bilinear transform, Engineering Science and Technology: an International Journal, 2015, doi:
10.1016/j.jestch.2015.08.008.
[14] J. Yli-Kaakinen and T. Saramaki, A systematic algorithm for the design of lattice wave digital filters with
short-coefficient wordlength, IEEE Trans. Circuits Syst. I, vol. 54, no. 8, pp. 1838-1851, Aug. 2007.
[15] L. Gazsi, Explicit formulas for lattice wave digital filters, IEEE Trans. on circuits and systems, vol. 32, no.
1, pp. 68-88, 1985.
[16] Henrik Ohlsson, Studies on implementation of digital filters with high
consumption, Thesis No. 1031, Linkping studies in science and technology, 2003.

throughput and low power

[17] http://www.mathworks.com/examples/matlab-hdl-coder/1311-constantmultiplierarea.

optimization-to-reduce-

[18] T. G. Noll, Carry save architectures for highspeed digital signal processing, J. VLSI Signal Processing, vol.
3, pp. 121-140, 1991.