MULTILEVEL MEMORIES

- To achieve a good trade-off between cost,

storage capacity and performance for
memory systems- multilevel memories are
used.
General Characteristics:
Consider a general n-level memory
system of n memory types.
Examples for n=2,3,4 are shown:

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Memory System
with n=2,3,4

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n=2 example for early computers.
n=3 adds a split cache; contains
separate area for storing data(D-Cache)
and instructions(I-Cache).
n=4 has two caches of unified type.
The relationship between these levels will
be:
Cost per bit: Ci > Ci+1
Access Time: ti > ti+1

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The CPU and other processors can
communicate with M1 only and M1 can
communicate with M2 and so on.
(i.e) For CPU to read data from some Mi level;
i data transfers are required.
The information stored in Mi at the given time
is also stored in Mi+1 but not vice versa.
For a memory hierarchy to work efficiently;
the addresses generated by CPU should be
found in M1 as often as possible.

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The CPU and other processors can
communicate with M1 only and M1 can
communicate with M2 and so on.
(i.e) For CPU to read data from some Mi level;
i data transfers are required.
The information stored in Mi at the given time
is also stored in Mi+1 but not vice versa.
If an address generated from program is
found in Mi where i>1; the address must be
relocated from Mi to M1 which is a slow process.

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For a memory hierarchy to work
efficiently; the addresses generated by CPU
should be found in M1 as often as possible.
(i.e addresses are predictable).
If the desired data is not found in M1 ,
then the program originating memory
request must be suspended until the
required data is relocated.

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Virtual Memory:
The address generated by the processor
will not specify the physical location in
memory here.
But it generates virtual or logical
addresses; which is mapped onto the
physical memory where the data is stored.
Mapping function can be implemented by
MMU(Memory Management Unit).

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Reasons for using Virtual Memory:
To free user programs to carry out storage
allocation.
To make programs independent of
configuration and capacity of physical
memory.
To achieve low access time and cost per
bit.

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Locality of reference:
The predictability of memory addresses
depends on a characteristic program called
locality of reference.
Instead of transferring a single instruction to
M1 ; it is more efficient to transfer a block of
consecutive instructions containing that
instruction in the form of pages.
Eg: 4000 MOV A,B
4009 MOV A,B
4003 ADD C
400C SUB B
4006 ADD D
400F BZ 4009

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The first three consecutive instructions
reflects spatial locality. (Consecutive memory
references are made between consecutive
addresses).
The next three consecutive instructions
consists of loop; where even though they are
far apart they are executed repeatedly high
reference to memories temporal locality.
By spatial or temporal means, we can store
the page in M1

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Cost and performance:
Goal- Achieve a performance close to that of
the fastest device, M1 and cost per bit of
cheapest device, Mn
The performance depends on following
factors:
1. The address-reference statistics.
2. Access time of each level.
3. Storage capacity of each level.
4. Size of pages.
5. Allocation Algorithm used.

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Performance Metrics:
i. Average cost per bit of memory.
ii. Hit ratio, H.
iii. Access Efficiency.
iv. Space Utilization.

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Regions of M1:
Empty Regions: Blocks of data occupying M1 is of
different length; as the contents are changed
empty regions arise. This phenomena is called
fragmentation.
Inactive Regions: Without being referenced by
the processor, the data in M1 may transferred
back to M2 those data regions are said to be
inactive.
System Regions: Occupied by memory
management software.

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MMU should do following tasks(to make it
appear like a single, fast memory of high
capacity)
1. Translation of virtual addresses to
physical addresses.
2. Dynamic allocation (swapping) of
information among different memory
levels.