A SCALABLE APPROXIMATE DCT

ARCHITECTURE FOR
EFFICIENT HEVC COMPLIANT VIDEO
CODING

ABSTRACT

An approximate kernel for the discrete cosine transform (DCT) of length 4

is derived from the 4-point DCT defined by the High Efficiency Video
Coding (HEVC) standard, and used that for the computation of DCT and
inverse DCT (IDCT) of power of -2 lengths.

There are two reasons to consider the DCT of length 4 as the basic
module. Firstly, it allows computing DCTs of length 4, 8, 16, and 32
prescribed by HEVC.

Cont,.

Moreover, the DCTs generated by 4-point DCT not only involve lower
complexity but also offer better compression performance.

Full-parallel

and

area-constrained

architectures

for

the

proposed

approximate DCT are proposed to have flexible trade-off between area and
time complexities.

Also, a reconfigurable architecture is proposed where 8-point DCT can be

used for a pair of 4-point DCTs.

Cont,.
Using the same reconfiguration scheme 32-point DCT could be configured
for parallel computation of two 16-point DCTs or four 8-point DCTs or eight
4-point DCTs.
The proposed approach can be Implemented using Verilog HDL and
Simulated by Modelsim 6.4 c.
Finally its Synthesized by Xilinx tool and Implemented in FPGA Spartan 3
XC3S 200 TQ-144.

EXISTING SYSTEM

An orthogonal approximation for the 8-point discrete cosine transform

(DCT) is introduced.

The proposed transformation matrix contains only zeros and ones;

multiplications and bit shift operations are absent.

Close spectral behavior relative to the DCT was adopted as design

criterion.

Cont,

The proposed algorithm is superior to the signed discrete cosine transform.

It could also outperform state-of-the-art algorithms in low and high image

compression scenarios, exhibiting at the same time a comparable
computational complexity.

EXISTING SYSTEM TECHNIQUE:

Orthogonal approximation for the 8-point discrete cosine transform (DCT)

EXISTING SYSTEM DRAWBACKS:

More Complexity

Less Area Efficiency

PROPOSED SYSTEM

A 4x4 approximate DCT matrix is proposed, and then used that for generating all
higher length DCTs.

It is advantageous to consider DCT of length 4 as the basic module and to generate

DCT of higher lengths using the 4-point DCT.

Firstly, it allows to compute DCTs of all the lengths 4, 8, 16, and 32 prescribed by
HEVC.

Moreover, the DCTs generated by 4-point approximate DCT not only involve lower
computational complexity but also offer better compression performance.

Full parallel architecture and area-constrained architecture are proposed, which

provide highly flexible trade-off between area and time complexities.

PROPOSED SYSTEM BLOCK DIAGRAM

PROPOSED SYSTEM ALGORITHM

A fully scalable approximate DCT

PROPOSED SYSTEM ADVANTAGES

Involves significantly less error energy

Provides better compressed image quality than the other approximate DCT

Increase in bit-rate

Hardware complexity is reduced

SOFTWARE REQUIREMENT

ModelSim6.4c

Xilinx 9.1/13.2

IMPLEMENTATION LANGUAGE:

Verilog HDL

HARDWARE REQUIREMENT

Spartan 3 XC3S 200 TQ-144

REAL TIME EXAMPLE

video compression
The proposed method can perform HEVC-compliant video coding
Mobile devices
Small smart systems connected to Internet of Things (IoT)
Coding, decoding, downloading, and displaying of video content are
the most commonly used functionalities in small mobile connected
devices

FUTURE ENHANCEMENT
We will reduce the Area with the help of Changing the Transpose Memory

ALTERNATE TITLES:
Title 1: An Efficient VLSI Implementation of scalable approximate DCT

architecture
Title 2: Design scalable approximate DCT architecture for Video Coding

Application
Title 3: FPGA Implementation of scalable approximate Discrete Cosine Transform

architecture