State Assignment Example

Design a clock synchronous sequential circuit

with two inputs A, B and a single output Z that
is 1 if:
A had the same value at each of the two previous
clock ticks, or
B has been 1 since the last time that the first
condition was true.
Otherwise, output should be 0.

Lecture
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State Assignment Example (cont.)

A: 0 1 0 0 1 1 1 0 0 1 1 0 1 0 1 1 0 0
B: 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0
Z: 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 0

State definitions:
INIT: initial state
A0: A had 10 but not 00 on
the previous clock ticks.
A1: A had 01 but not 11 on
the previous clock ticks.
OK0: A had 00, or when OK B=1 and last A=0
OK1: A had 11, or when OK B=1 and last A=1
Lecture
17 of Engineering
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How to choose the best state assignment?

Formal way: try all assignments!
To much work, not practical.

Guidelines for reasonable state assignments:

Choose an initial state into which the machine can easily be forced at reset
(000 or 111).
Minimize the number of state variables that change on each transition.
Maximize the number of state variables that dont change in a group of
related states.
Exploit symmetries in the problem specifications.
Dont limit the choice of coded states to the first m n-bit integers.
Decompose the set of state variables into individual bits or fields, where
each bit or field has a well-defined meaning wrt the input effects or output
behavior.
Consider using more than the minimum number of state variables to
make, a decomposed assignment, possible.

Lecture
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Ex: Decomposed State Assignment

State

Q1Q2Q3

INIT

000

A0

100

A1

101

OK0

110

OK1

111

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Easy to force reset state

When Q1=1
Q2 indicates an OK state
Q3 indicates the previous
value of A

Ex: One-hot State Assignment

State

Q1Q5

Q1Q4
(almost one-hot)

INIT

00001

0000

A0

00010

0001

A1

00100

0010

OK0

01000

0100

OK1

10000

1000

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One bit to each state

Simple structure
Requires more than
minimum number of
FFs.

Note on unused states

Minimal Risk:
Consider getting one of the unused (or illegal) states (can be
hardware failure, design error, etc).
Identify unused states, create next-state transitions to initial, idle or
a safe state.

Minimal Cost:
Assumes the machine never enters to the unused states.
In the next-state table unused states can be marked as dont cares.
Simplifies excitation logic, but may create problems.

Lecture
17 of Engineering
KU College

State Minimization
Should minimize the cost of the final sequential
clocked circuit (scct) either by
Reducing the number of gates, or
Reducing the number of FFs

One possible way for this minimization is

Elimination of equivalent states.

Equivalent states:
If it is impossible to distinguish them by observing the
current and future outputs of the machine.

Lecture
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 Example on equivalent states:

Present
State

EG
FD
Present
State

Next State
X=0 X=1

Output
X=0
X=1

Next State
X=0 X=1

Output
X=0 X=1

Lecture
17 of Engineering
KU College

Other Flip-Flop Types

J-K and T flip-flops
Behavior
Implementation

Basic descriptors for understanding and using

different flip-flop types
Characteristic tables
Characteristic equations
Excitation tables
For actual use, see Reading Supplement - Design and
Analysis Using J-K and T Flip-Flops
Lecture
17 of Engineering
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J-K Flip-flop
Behavior

Same as S-R flip-flop with J analogous to S and K analogous to R

Except that J = K = 1 is allowed, and
For J = K = 1, the flip-flop changes to the opposite state
As a master-slave, has same 1s catching behavior as S-R flipflop
If the master changes to the wrong state, that state will be passed
to the slave
E.g., if master falsely set by J = 1, K = 1 cannot reset it during the
current clock cycle

Lecture
17 of Engineering
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10

J-K Flip-flop (continued)

Implementation

Symbol

To avoid 1s catching
behavior, one solution
used is to use an
edge-triggered D as
the core of the flip-flop

J
C
K

J
K

D
C

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11

T Flip-flop
Behavior
Has a single input T
For T = 0, no change to state
For T = 1, changes to opposite state

Same as a J-K flip-flop with J = K = T

As a master-slave, has same 1s catching behavior as J-K
flip-flop
Cannot be initialized to a known state using the T input
Reset (asynchronous or synchronous) essential

Lecture
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12

T Flip-flop (continued)

Implementation

Symbol

To avoid 1s catching
behavior, one solution
used is to use an
edge-triggered D as
the core of the flip-flop

Lecture
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13

Basic Flip-Flop Descriptors

Used in analysis
Characteristic table - defines the next state of the flipflop in terms of flip-flop inputs and current state
Characteristic equation - defines the next state of the
flip-flop as a Boolean function of the flip-flop inputs
and the current state

Used in design
Excitation table - defines the flip-flop input variable
values as function of the current state and next state

Lecture
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14

D Flip-Flop Descriptors
Characteristic Table
D

Q(t+1) Operation

0
1

0
1

Reset
Set

Characteristic Equation
Q(t+1) = D
Excitation Table
Q(t+1)
0
1

Operation

0
1

Reset
Set

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T Flip-Flop Descriptors
Characteristic Table
T Q(t+1) Operation
0

Q(t)

No change

Q(t)

Complement

Characteristic Equation
Q(t+1) = T Q
Excitation Table
Q(t 1)

Operation

Q(t)

No change

Q(t)

Complement

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16

S-R Flip-Flop Descriptors

Characteristic Table

S R Q(t+1) Operation
0 0
0 1
1 0

Q(t)
0
1

1 1

No change
Reset
Se
t
Undefined

Characteristic Equation
Q(t+1) = S + R Q, S.R = 0
Excitation Table

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Q(t) Q(t+1) S R Operation

0
0
1

0
1
0

0 X No change
1 0 Set
0 1 Reset

X 0 No change
17

J-K Flip-Flop Descriptors

Characteristic Table

J K Q(t+1) Operation

Characteristic Equation
Q(t+1) = J Q + K Q

Excitation Table

0
0
1
1

0
1
0
1

Q(t)
0
1
Q(t)

No change
Reset
Set
Complement

Q(t) Q(t+1) J K Operation

0
0
1
1

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0
1
0
1

0
1
X
X

X
X
1
0

No change
Set
Reset
No Change
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Flip-flop Behavior Example

Use the characteristic tables to find the output waveforms for the flipflops shown:
Clock
D,T

QD

D
C

QT

T
C

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19

Flip-Flop Behavior Example (continued)

Use the characteristic tables to find the output waveforms for the flipflops shown:
Clock
S,J
R,K

S
C
R

QSR

QJK

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17 of Engineering
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