Professional Documents
Culture Documents
Sequential Logic
Latches & Flip-flops
Introduction
Memory Elements
Pulse-Triggered Latch
S-R Latch
Gated S-R Latch
Gated D Latch
Edge-Triggered Flip-flops
S-R Flip-flop
D Flip-flop
J-K Flip-flop
T Flip-flop
Asynchronous Inputs
2
Introduction
Memory outputs
Combinational
logic
Memory
elements
External inputs
Comparison
Introduction
Comparison
In synchronous circuits,
memory elements are
clocked FFs
In synchronous circuits, the
change in input signals can
affect memory elements
upon activation of clock
signal.
The maximum operating
speed of the clock depends
on time delays involved
Easier to design.
In asynchronous circuits,
memory elements are either
unclocked FFs or time delay
elements
In asynchronous circuits,
change input signals can
affect memory elements at
any instance of time
Because of the absence of
the clock, asynchronous
circuits can operate faster
than synchronous circuits.
More difficult to design.
Memory Elements
command
stored value
Characteristic table:
Command
(at time t)
Q(t)
Q(t+1)
Set
Reset
Memorise /
No Change
0
1
0
1
Memory Elements
command
stored value
clock
Positive edges
Negative edges
8
Memory Elements
Pulse-triggered
latches
ON = 1, OFF = 0
Edge-triggered
flip-flops
positive edge-triggered (ON = from 0 to 1; OFF = other
time)
negative edge-triggered (ON = from 1 to 0; OFF = other
time)
9
S-R Latch
S-R Latch
10
S-R Latch
S-R Latch
11
S-R Latch
Q'
NC
NC
1
0
1
0
1
1
1
0
0
0
1
0
No change. Latch
remained in present state.
Latch SET.
Latch RESET.
Invalid condition.
Q'
R'
Q'
NC
NC
0
1
0
1
0
0
1
0
1
0
1
1
No change. Latch
remained in present state.
Latch SET.
Latch RESET.
Invalid condition.
S-R Latch
Q'
12
S-R Latch
Active-HIGH input S-R latch
10 100 R
Q 11000
10 001 S
Q' 0 0 1 1 0
S'
R'
S
1
0
0
0
1
R
0
0
1
0
1
Q Q'
1 0
initial
1 0 (afer S=1, R=0)
0 1
0 1 (after S=0, R=1)
0 0
invalid!
S'
R'
Q
Q'
S-R Latch
S' R'
1 0
1 1
0 1
1 1
0 0
Q Q'
0 1
initial
0 1 (afer S'=1, R'=0)
1 0
1 0 (after S'=0, R'=1)
1 1
invalid!
13
EN
EN
Q'
Q'
14
Characteristic table:
EN=1
Q(t)
Q(t+1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
indeterminate
1
0
1
indeterminate
S R
0
0
1
1
0
1
0
1
Q(t+1)
No change
Q(t)
0
Reset
1
Set
indeterminate
Q(t+1) = S + R'.Q
S.R = 0
15
Gated D Latch
EN
EN
Q'
Gated D Latch
Q'
16
Gated D Latch
When EN is HIGH,
D=HIGH latch is SET
D=LOW latch is RESET
Characteristic table:
EN
Q(t+1)
1
1
0
0
1
X
0
1
Q(t)
Reset
Set
No change
Gated D Latch
17
18
Edge-Triggered Flip-flops
Negative edges
Edge-Triggered Flip-flops
19
Edge-Triggered Flip-flops
C
R
C
Q'
C
Q'
Q'
C
R
C
Q'
C
Q'
Q'
20
S-R Flip-flop
CLK
Q(t+1)
Comments
0
0
1
1
0
1
0
1
Q(t)
0
1
?
No change
Reset
Set
Invalid
21
S-R Flip-flop
It comprises 3 parts:
a basic NAND latch
a pulse-steering circuit
a pulse transition detector (or edge detector) circuit
SR Flip-flop
22
S-R Flip-flop
The pulse transition detector.
S
Pulse
transition
detector
CLK
Q'
CLK'
CLK
CLK'
CLK*
CLK
CLK*
CLK
CLK
CLK'
CLK'
CLK*
CLK*
Positive-going transition
(rising edge)
Negative-going transition
(falling edge)
SR Flip-flop
23
D Flip-flop
C
R
CLK
Q(t+1)
1
0
1
0
Comments
Set
Reset
Q'
= clock transition LOW to HIGH
24
D Flip-flop
Combinational
logic circuit
CLK
D
Transfer
CLK
Q1 = X*
Q'
Q
Q2 = Y*
Q'
Q
Q3 = Z*
Q'
25
J-K Flip-flop
J-K flip-flop: Q and Q' are fed back to the pulsesteering NAND gates.
No invalid state.
J-K Flip-Ffop
26
J-K Flip-flop
J-K flip-flop.
J
Q
Pulse
transition
detector
CLK
Q'
Characteristic table.
J
CLK
Q(t+1)
Comments
0
0
1
1
0
1
0
1
Q(t)
0
1
Q(t)'
No change
Reset
Set
Toggle
J K
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q(t+1)
0
0
1
1
1
0
1
0
27
T Flip-flop
CLK
CLK
Q'
Q'
Characteristic table.
T
CLK
Q(t+1)
Comments
Q T
0
1
Q(t)
Q(t)'
No change
Toggle
0
0
1
1
0
1
0
1
Q(t+1)
0
1
1
0
28
T Flip-flop
High
J
CLK
High
CLK
K
CLK
CLK
QA
QA
QB
QB
29
Asynchronous Inputs
Asynchronous Inputs
30
Asynchronous Inputs
PRE
J
CLK
Q'
Q
Pulse
transition
detector
Q'
K
CLR
CLR
CLK
PRE
CLR
J = K = HIGH
Preset
Asynchronous Inputs
Toggle
Clear
31
End of segment