UNIT - I

VLSI
FABRICATION
TECHNIQUES

Silicon Wafer fabrication

Silicon wafer (Substrate) preparation

Epitaxial Growth
Oxidation
photolithiography
Diffusion
Ion Implementation
Isolation Technique
Metallization
Assembly Processing and packaging

Silicon wafer (Substrate)

preparation
The following steps are used in the
preparation of Si-wafers
1.crystal growth and doping
2.Ingot trimming and grinding
3.Ingot slicing
4.Wafer polishing and etching
5.Wafer cleaning

czochralski crystal growth

starting material for crystal growth is highly purified

(99.9999) polycrystalline silicon.
czochralski crystal growth process for producing single
crystal silicon ingots
polycrystalline silicon together with an appropriate amount of
dopant is put in a quartz Crucible and is then placed in a
furnace
material is then heated to a temperature in excess of the
silicon melting point of 1420 degree Celsius.
A small single crystal rod of silicon called a seed crystal is
then dipped into the silicon melt slowly pulled.
As the seed crystal is pulled out of the melt it brings with it a
solidified mass of silicon with name crystalline structure as
that of seed crystal.
During the crystal pulling process the seed crystal and the
crucible are rotated in opposite directions in order to produce
ingots of circular cross section the diameter of about 10 to 15
cm and ingot length order of 100 cm

czochralski crystal growth

czochralski crystal growth

top and bottom portions of the ingot are cut off

and ingot surface is ground to produce an exact
diameter

The ingot is then sliced using a stainless steel

saw blade with industrial diamonds embedded
into the inner diameter cutting edge.

This produces circulars wafers or slices.

EPITAXIAL GROWTH
epi

means upon
teinon means arranged .
arranging atoms in single crystal
fashion upon a single crystal substrate
so resulting layer is an extension of the
substrate crystal structure.
Chemical process-Hydrogen reduction

SYSTEM

OXIDATION

SiO2 has the property of preventing diffusion of almost all

impurities through it.
It serves very important purposes.
Formation of sio2 layer
SiO2 is an extremely hard protective coating and is
unaffected by almost all reagents except hydrofluoric acid .
Thus it stands against any contamination
Thermal oxidation technique (High temperature 950-1115
Celsius)
By selective etching of SiO2 difussion of impurities through
carefully defined Windows in the SiO2 can be accomplished
to fabricate various components.
Thickness of oxide layer

types
Wet Oxidation:
oxidizing atmosphere contains water vapor at
temperatures between 900 to1000Celcius.
Very rapid process. Used for thick field oxides.

Si 2 H 2O SiO2 2 H 2

Dry Oxidation:
oxidizing atmosphere is pure oxygen at
temperatures of 1200C.
Produces better quality oxide than wet oxidation.
Used for thin, highly controlled oxides.

Si O2 SiO2

Patterning - Photolithography

The patterning is achieved by a process called

photolithography.
Possible to produce microscopically small circuit
and device patterns on Si wafers
10000 transistors can be fabricated on a 1cm * 1cm
chip .
the conventional photolithographic process uses
ultraviolet light exposure
device dimension or line width as small as 2
micrometer can be obtained .
using X rays or electron beam lithographic
techniques it has become possible to produce
device dimension down to submission range <1
micro meter

It involves two process

Making

of a
photographic mask

Photo

etching

Masks are used to define the different regions in the device.

Masks are created using data provided by the layout engineer.
Mask are used to isolate regions, the properties of which are
either changed or kept the same during various processing
steps in contrast to the regions not covered by the mask.
The regions of interest are defined on wafer using a materials
called photoresist.
The wafer is coated with the photoresist and subjected to
selective illumination through the photomask.
A photomask is constructed with chromium (chrome) covered
quartz glass.
A UV light source is used to expose the photoresist. The
photomask has chrome where light should be blocked.
The organic photoresist is exposed to the light in regions where
the chrome is not present.
developer solvent is used to dissolve the soluble unexposed
photoresist, leaving islands of insoluble exposed photoresist.
Called negative photoresist.
A positive photoresist is initially insoluble, and when exposed
to UV becomes soluble.

Making of a photographic
mask

Initial art work

Reduction
Opaque region(thin layer - Rubyligth)
Coordinotograph
Drawing the layer patterns on a layout editor
Masks generation from the layer patterns in the design data base
Printing: transfer the mask pattern to the wafer surface
Process the wafer to physically pattern each layer of the IC

Etching

Wafer is coated with film of photo sensitive

emulation (Kodak photo resist-KPR)
Thickness
Exposed to UV light
KPR becomes polymerized beneath the
transparent region of mask
Mask removed and wafer formed by using
trichloroethylene
Immersed in hydrofluoric acid which
removes sio2 layer not protected by KPR

types
Wet

etching
above process
(chemical regents used in liquid form)

Dry

etching (gas form)

Mostly used
Smaller line opening

DIFFUSION

Diffusion

of impurities in chip
Ptype doping-boron
Ntype doping-Phosphorous-

ION IMPLATATION

 Silicon

wafers placed in vacuum chamber

Scanned by high energy dopant ions
20kv-250 kv
Depth of penetration controlled by
accelerating voltage
ISOLATION
Provide isolation between two electrical
components
2 types

PN junction isolation

Economical
Capacitance reduce the performance in high
frequencies

DIELECTRIC ISOLATION

Isolation

material used silicon dioxide or

ruby
Professional grade ics
Required additional fabrication step
Cost high

METALLIZATION

 Interconnection
Aluminum

used

of various components

 Scrubbing

and cleaving
Separating individual chips
TO-5

class metal package

Assembly Processing and

packaging

Ceramic flat package

Dual in line package (normal ic)

CMOS Fabrication
Process
CMOS can be fabricated using different
processes
N-well process for CMOS fabrication
P-well process
Twin tub-CMOS-fabrication process
Silicon On Insulator (SOI)

N Well process
Step1:

Substrate
Primarily, start the process with a Psubstrate.
Step2: Oxidation
The oxidation process is done by using
high-purity oxygen and hydrogen, which
are exposed in an oxidation furnace
approximately at 1000 degree centigrade.

 Step3:

Photoresist
A light-sensitive polymer that softens
wheneverexposed to light is called as
Photoresist layer. It is formed.

Step4:

Masking
The photoresist is exposed to UV rays
through the N-well mask

 Step5:

Photoresist removal
A part of the photoresist layer is removed by
treating the wafer with the basic or acidic
solution.

Step6:

Removal of SiO2 using acid etching

The SiO2 oxidation layer is removed through
the open area made by the removal of
photoresist using hydrofluoric acid.

 Step7:

Removal of photoresist
The entire photoresist layer is stripped off, as
shown in the below figure.

Step8:

Formation of the N-well

By using ion implantation or diffusion process Nwell is formed.

 Step9:

Removal of SiO2
Using the hydrofluoric acid, the remaining
SiO2 is removed.

Step10:

Deposition of polysilicon

 Step11:

Removing the layer

barring a small area for the Gates

Step12:

Oxidation process
Next, an oxidation layer is formed on
this layer with two small regions for the
formation of the gate terminals of NMOS
and PMOS.

 Step13:

Masking and N-diffusion

By using the masking process small
gaps are made for the purpose of Ndiffusion

The

n-type (n+) dopants are diffused or

ion implanted, and the three n+ are
formed for the formation of the
terminals of NMOS.

 Step14:

Oxide stripping
The remaining oxidation layer is
stripped off.

Step15:

P-diffusion
Similar to the above N-diffusion process,
the P-diffusion regions are diffused to
form the terminals of the PMOS.

 Step16:

Thick field oxide

A thick-field oxide is formed in all
regions except the terminals of the
PMOS and NMOS.

Step17:

Metallization
Aluminum is sputtered on the whole
wafer.

 Step18:

Removal of excess metal

The excess metal is removed from the
wafer layer.

Step19:

Terminals
The terminals of the PMOS and NMOS
are made from respective gaps.

 Step20:

Assigning the names of the

terminals of the NMOS and PMOS
Substrate must be
Tied to gnd
Nwell to Vdd

P well
P-well

process is almost similar to the Nwell. But the only difference in p-well
process is that it consists of a main Nsubstrate and, thus, P-wells itself acts as
substrate for the N-devices.

Twin tub-CMOS
Fabrication Process

n this process, separate optimization of the n-type and ptype transistors will be provided. The independent
optimization of Vt, body effect and gain of the P-devices, Ndevices can be made possible with this process.

steps of the fabrication of

the CMOS - twintub
Lightly doped n+ or p+ substrate is
process
taken and, to protect the latch up,
epitaxial layer is used.
The high-purity controlled thickness of
the layers of silicon are grown with
exact dopant concentrations.
The dopant and its concentration in
Silicon are used to determine electrical
properties.

 Formation

of the tub
Thin oxide construction
Implantation of the source and drain
Cuts for making contacts
Metallization

steps

Twintub process cross

section view

Silicon On Insulator (SOI)

Silicon

On Insulator (SOI) Fabrication

technology Transistors are built on a
silicon layer resting on an Insulating
Layer of Silicon dioxide (SiO2).
The insulating layer is created by
flowing oxygen onto a plain silicon wafer
and then heating the wafer to oxidize
the silicon, thereby creating a uniform
buried layer of silicon dioxide.

 Transistors

are encapsulated in SiO2 on

all sides.
The blow figure shows a typical
NMOS Transistor with Bulk CMOS
Process and with SOI Process.

 The

insulating layer increases device

performance by reducing junction
capacitance
as the junction is isolated from bulk silicon.
The decrease in junction capacitance also
reduces overall power consumption.

Isotropic

etching is used

Etching types
Isotropic etch
Fully anisotropic
etch
Prefential etch

SOI process

Advantages :
20% to 50% increase in switching speed compared to
similar circuits built on conventional "bulk" silicon
wafers
the ability to operate at lower voltages (less battery
power drain and chip heating)
events from cosmic ray particle showers (reducing the
need for error correction operations in high-speed data
flow servers and memory arrays)
increased circuit packing due to simplification of the
lateral and vertical isolation structures, increasing chip
yield and die count per wafer
Disadvantage
Most expensive

CMOS Process
Enhancement
To

increase routability
To provide high quality capacitors for analog
circuits and memory
To provide resistors of variable characteristics
process include
Double

or triple level metal

Double or triple level poly

Interconnects
connections between transistors are primarily

The

done using a metal such as aluminum or copper

and these wires are known as interconnects.
additional signal and power routing layers
routing of logic signals between modules and
improves the power and clock distribution to
modules
Improved routability is achieved through
additional layers of metal or by improving the
existing polysilicon interconnecting layer
number of layers of interconnect earlier 2 layers
10 layers now

 fabrication

of interconnect begins - the first metal

layer and that is used to make contact with
transistor source, drain and gate terminals and to
connect them to nearby V DD , ground and
input/output of other transistors.
The different levels of metals are connected to
each other using contacts or vias.
Generally speaking contacts are used to connect
wires to transistors
while vias are used to connect one metal layer to
another.
upper layers of metal are used for global signals,
clock and power distribution and must carry large
amounts of currents. The cross sections are mad
relatively large to keep the resistance levels low.

The lower levels for block level and cell level

routing and are kept small for high density.
problem in fabricating multi layer interconnects
as layers are placed one over another the surface
becomes uneven and this may lead to stresses and
strains in structure.
Before a new layer of metal is placed on the chip,
the surface must be planarized
In the past aluminum was used for the metal layers
and tungsten was used to implement vias.
Due to increase in resistance and electro migration
problems copper is introduced to replace aluminum.
copper diffuses rapidly in silicon titanium nitrate is
used to surround copper to prevent diffusing into
SiO2 .

Resistors in CMOS
Technology

Resistors include diffused, poly-silicon and well

resistors.
The diffused layer that used to form the source
and drain of MOS devices can be used to form a
diffused resistor.
Similarly the polysilicon required in silicon gate
MOS technology can be used to form resistors.
The nominal sheet resistance is in the order of
20 / to 80 / . To reduce the sheet resistance
a silicide layer is deposited on the top of the
polysilicon.

 The

well region in the CMOS technologies can also

be used as resistors.
It is relatively lightly doped region and this
resistor provides a sheet resistance of the order of
10k / .
The MOS transistor biased in the triode region can
be used in many circuits to perform the function
of a resistor. In the drain-source resistance
calculated by differentiating the drain current in
the triode region with respect to the drain-source
voltage.
The principal disadvantage of this form of resistor
is its non-linearity. That is the resistance is not
constant, but depends on the drain-source voltage

Capacitors
Capacitors in CMOS technology include poly-poly,
metal-poly, silicon-silicon and vertical and lateral
metal-metal.
analog functions have two layers of poly silicon.
second layer an extra layer of inter connect, and
also to implement floating gate memory cells that
are electrically programmable and optically erasable
with UV light.
An important aspect of the capacitor structure is the
parasitic capacitance associated with each plate.
This bottom plate parasitic capacitance is typically
ten to 30 % of the capacitor itself.

Latch-up
Parasitic

circuit effect is called Latch up

Result of this effect vdd and vss shortened
Result in self destruction or system failure
Power down
These transistors can be activated in various
ways and as CMOS technologies are scaled down,
this variety grows.
proper process and lay out
design, CMOS chips
can be operated
without ever encountering
latch up.

controlling latch up
bipolar

spoiling and bipolar decoupling.

bipolar spoiling
(i)doping silicon with gold or neutron irradiation
to reduce the base minority carrier life time.
(ii) spoiling the gain -build into the base a
retarding electric field - achieved by using
well, i.e. doping increases in going downward
from emitter to collector.
(iii) use of schottky barrier source/drains and
thus reducing the emitter injection efficiency.

 Bipolar

decoupling
highly doped substrate beneath a lightly doped
epi-layer very effectively shunts the lateral
parasitic bipolar. Reverse bias on the substrate
(or well) raises the bypass current needed to
turn on corresponding bipolar.