Background for

Leakage Current
Sept. 18, 2006

Power Challenge
Active power density increasing with

device scaling and increased frequency

Leakage power density increasing due
to lower Vt and gate leakage
Stressing packaging, cooling, battery
life, etc.
Complicates IDDq testing as well

Source from Bergamaschi

Thinning gate oxides

increase
gate tunneling leakage

Problem Statement
Power Analysis on CMOS Inverter

Input s w itching to '1 ' or '0'

V thn < Input < V DD- | V thp |

Input : '1 ' or '0' s te ady s tate

char g e
Input

Input

Input

Cload
dis char g e

(a) Capacitiv e Cur r ent

(b) Shor t Cir cuit Cur r ent

(c) Static L e ak ag e Cur r ent

Problem Statement
Dynamic Power
Pswitching Cswitching VDD 2 f

Average Short Circuit Current

I SC

in

(VDD 2Vth ) 3 f
12 VDD
gain _ factor: n p ,
Threshold _ Voltage: Vthn Vthp Vth

Sub-threshold Leakage Current

I DS e (VGS Vth )q / nkT (1 e VDS q / kT )
K: function of technology, VGS : gate to source voltage, VDS : drain to source voltage,
Vth : theshold voltage, q: electronic charge, k : Boltzmann constance, T: temperature,
n: nonlinearity constance 1 ~ 2 , ( kT 0.0259)

Problem Statement
Domination of Leakage Current
Feature
FeatureSize
Size

>>0.25um
0.25um

0.18/0.13/0.09um
0.18/0.13/0.09um

Performance(AP)
Performance(AP)

<<200MHz
200MHz

300/400/533MHz,
300/400/533MHz,1GHz
1GHz

Core
CoreVoltage
Voltage

5.0/3.3/2.5V
5.0/3.3/2.5V

1.8/1.2/1.0V
1.8/1.2/1.0V

VVTH(Threshold)
TH(Threshold)

>>+/+/-0.6V
0.6V

+/+/-0.5,
0.5,0.4,
0.4,0.3V
0.3V

TR
TRLeakage
Leakage

Negligible
Negligible

Exponential
Exponentialgrowing(SD/Gate)
growing(SD/Gate)

Stand-by
Stand-byMode
Mode

PLL-off(Clock-off)
PLL-off(Clock-off)

V/MTMOS,
V/MTMOS,High
HighVVTHTH/High
/HighVDD
VDD

Low
LowPower
Power

Focus
Focuson
onOperating
OperatingPower
Power

Focus
Focuson
onOperating/Stand-by
Operating/Stand-by

Active and Leakage Power with CMOS

Scaling
As CMOS scales down the
following stand-by leakage
current rises rapidly.
Source to drain leakage
(diffusion+tunneling) as
Lg scales down
Gate leakage current
(tunneling) as Tox scales
down
Body to drain leakage
current (tunneling) as
channel doping scales up

Two cases of Leakage Mechanism

Turn of

Turn on

Sub-threshold Leakage
Source to drain tunneling

Vg=0V
Vd=Vdd

Drain to Body tunneling

(BTB)

Vg=Vdd
Vd=0V

Gate oxide
tunneling

Current Density (A/cm)

Gate Leakage Current Reduction with HighK Gate Dielectric

1

10

10

-1

10

Drain leakage

-2

10

-3

10

Gate leakage

-4

10

Cox

-5

10

-6

10

20

25

High-K gate dielectric

k0 A
Tphysical
30

Tox (A)

35

40

Voltage Scaling for Low Power

Low Power

P VDD2

Low
Low VDD
VDD
I ds (VDD - Vth)1~2

Low Speed
Speed Up

I leakage e-C x Vth

Low
Low VVthth
High Leakage
Leakage
Suppression

I ds (VDD - Vth)1~2

Low-Leakage Solution Technology

100

VTH control

Dynamic power[W]

VDD control
High speed

10

MTCMOS

High speed

VDD: 1.5V
VDD control
1

VDD: 1.0V
Low speed

VTH control

Low speed

VTH: 0.5V
100n
1p

10p

VTH: 0.25V
100p

1n

10n

Leakage power[W]

100n

VTCMOS & MTCMOS

Multi-Threshold
Multi-ThresholdCMOS
CMOS

Variable-Threshold
Variable-ThresholdCMOS
CMOS

SchematicDiagram
Diagram principle
principle Merit
Merit Demerit
Demerit
Schematic

VDD
VDD
Low-Vth

Sleep

Hi-Vth

N-well

Low Vt

GND

P-well

Vpb = VDD
or V+

Vt
Control
circuit

Vnb = 0 or V-

GND

On-off
On-offcontrol
controlofofinternal
internal
VDD
or
VSS
VDD or VSS
Special
SpecialF/Fs,
F/Fs,Two
TwoVths
Vths

Threshold
Thresholdcontrol
controlwith
withbulk-bias
bulk-bias
Triple
well
is
desirable
Triple well is desirable

Low
Lowleakage
leakageininstand-by
stand-bymode.
mode.
Conventional
design
Env.
Conventional design Env.

Low
Lowleakage
leakageininstand-by
stand-bymode.
mode.
Conventional
design
Env.
Conventional design Env.

Large
Largeserial
serialMOSFET
MOSFET
ground
groundbounce
bouncenoise
noise
Ultra-low
voltage
region?(1V)
Ultra-low voltage region?(1V)

Scalability?
Scalability?(junction
(junctionleakage)
leakage)
TR
reliability
under
0.1m
TR reliability under 0.1m

Latch-up immunity, Vth controllability,

Latch-up immunity, Vth controllability,
Substrate
Substratenoise,
noise,Gate
Gateoxide
oxidereliability
reliability

Gate
Gateleakage
leakagecurrent
current

MTCMOS : Reduce Stand-by Power with

High Speed

With High VTH switch (MTCMOS)

Without High VTH switch

Vdd

Vdd
Normal or Low VTH MOSFET

Virtual Ground
Vss

0
Vss
High VTH switch

With High VTH switch, much lower leakage current flows between Vdd and Vss
High VTH MOSFET should have much lower ( >10X) leakage current compared to normal V TH
MOSFET

Multi-Threshold CMOS (MTCMOS)

Mobile Applications
Mostly in the idle state
Sub-threshold leakage Current
Power Gating
Low VTH Transistors for High Performance Logic Gates
High VTH Transistors for Low Leakage Current Gates

Current
Logic
Component Cutoff-Switch
(High Vth)
(Low Vth)
Operating
Mode Active
Sleep
Control
(SC)

VDD
Sleep

Low Vth
MOS

Active
SC

Time

VGND
VSS

High Vth
MOS

CCS Sizing
The effect of CCS (current-controlled switch) size
As the size decreases, logic performance also decreases.
As the size increases, leakage current and chip area also
increase.
Proper sizing is very important.
CCS size should be decided within 2% performance degradation.

VDD
Low Vt

Switch
Control

High Vt

GND

Vop = VDD - V
V must be sized

within 2% performance degradation

Leakage Current :
Limiting Factor in VDSM
Technology
C.M.Kyung

ITRS roadmap
Scaling down allows the same performance with reduced
voltage, leading to low power.
From 0.18 micron down, building a transistor with a good
active current(Ion) and a low leakage current (Ioff) is
difficult.
high-speed TRs ; low channel doping
low-leakage TRs ; high channel doping

Now three groups of TRs;

High Performance (HP) ; high active current ; Thin Tox
Low Operating Power (LOP) ; low active current ; High Tox
Low Standby Power (LSTP) ; low static current ; High Tox

Device characteristics for HP, LOP, and LSTP Technologies

Bulk CMOS vs. SOI

Buried oxide layer below active silicon layer
-> electrical isolation of TRs
Lower parasitic cap.

PD(Partially Depleted)
Floating body effect increases speed
Low threshold in dynamic mode

or FD(Fully Depl)
Ideal subthresold swing of 60 mV/decade

Reducing Subthreshold current in

Bulk CMOS
VTCMOS (Variable Threshold)

Tune substrate bias to adjust Vth

Requires efficient DC-DC converter
For a given technology, there an optimum in VR , as decreasing
subthreshold leakage is accompanied by an increase in drain
junction leakage

When both High Vt and Low Vt TRs are available,

MTCMOS (Multi-Threshold) ; Introduce high Vt power switch to

limit leakage in stby mode
Use low Vt for critical path
This can be coupled with multiple VDDs

Other tricks

Set up the logical internal states where the total leakage is

minimal.

Five types of off-currents

Tunneling through gate oxide
Fowler-Nordheim tunneling -> direct tunneling

Subthreshold current
Gate-induced drain leakage (GIDL)
Thermal emission
Trap-assisted tunneling
BTBT

Reverse-biased pn junction current

-> band-to-band tunneling (BTBT) current

Bulk punch-through

Gate-induced drain leakage (GIDL)

Gate-induced drain leakage (GIDL)
Thermal emission
Trap-assisted tunneling
BTBT

Fig 3.12

Leakage current due to

QM Tunneling
substrate and drain ; band-to-band tunneling ;

increases with E-field and dopant concentration due to

scaling

source and drain ;

Surface punchthru due to DIBL

Punch-through at bulk

gate oxide ;

SiO2 has been used as it has so low trap and fixed

charge density at the interface
Gate current is an exponential function of Tox and Vox
Hole tunneling is 10% of that of electron due to higher
barrier height and heavier effective mass

Gate Leakage Current Reduction with HighK Gate Dielectric

As Tox scales gate leakage current increases
exponentially due to exponential increase of tunneling
probability with reduction of physical tunneling
distance.
Physically thicker gate dielectric allows lower leakage
current but lower oxide capacitance reducing on-current
Using high k (dielectric constant) material, both
thicker physical thickness and higher oxide
capacitance can be achieved.
Applying high-k gate dielectric, several orders of
magnitude lower gate leakage current can be achieved
with similar oxide capacitance

Approach 1 to reduce gate

leakage ; High K materials
To suppress gate tunneling current, use
materials with
High K -> increases thickness (t)
Higher barrier height (h)

Using high K
Increases short-channel effects due to thicker gate
dielectric (This sets an upper limit on K, lower limit
coming from I tunnel)
Mobility degradation due to poor interface quality

Approach 2 to reduce gate leakage ; stop

scaling the thickness of gate oxide
Thicker gate oxide yields less control of
gate on channel conduction, i.e., higher
short-channel effects and DIBL effects.

Approach 3 to reduce gate leakage

Multiple gates allows better control of
channel by gate, and lets scaling continue
without excessive short-channel effects
Double gate
FinFET
Triple gate
Quadruple or gate all-around