Digital To Analogue

Converter

DAC
1

Most real-world information is analog. For instance, time, speed, weight,

pressure, light intensity, and position measurements are all analog in
nature.
The digital system in Figure 6.1 has an analog input. The voltage varies
continuously from 0 to 3 V.
Analog
input
03V

Encoder
(A/D Converter)

Digital
Processing
unit

Decoder
(D/A Converter)

Analog
output
03V

Figure 6.1: A digital system with analog input and analog output

The encoder is a special device that converts the analog signal to digital
information. The encoder is called an analog-to-digital converter or, for
short, an A/D converter. The A/D converter, then, converts analog
information to digital data.
The digital system block diagram in Figure 6.1 also has a decoder. This
decoder is a special type; it converts the digital information from the digital
processing unit to an analog output. For instance, the analog output may
be a continuous voltage change from 0 to 3 V.
We call this decoder a digital-to-analog converter or, for short, a D/A
converter. The D/A converter, then, decode digital information to analog
form.

A block diagram of a D/A converter is shown in Figure 6.2.

The digital inputs (D, C, B, A) are at the left. The decoder consists of two
sections: the resistor network and the summing amplifier. The output is
shown as a voltage reading on the voltmeter at the right.

ANALOG OUTPUT

Figure 6.2: A block diagram of a D/A converter

Basically, D/A conversion is the process of taking a

value represented in digital code (such as straight
binary or BCD) and converting it to a voltage or
current which is proportional to the digital value as
shown in Table 6.1.
Figure 6.3 shows the symbol for a typical 4-bit D/A
converter.
MSB
D

Digital
inputs

D/A
converter
(DAC)

C
B

VOUT
Analog
output

A
LSB

Figure 6.3: Symbol of a D/A converter

VOUT

10

11

12

13

14

15

Table 6.1

volts

volts

METHOD OF CONVERSION
There are several methods and circuits for producing the D/A operation
that has been described. We shall examine several of the basic schemes
to gain and insight into the ideas used.
One method of the D/A conversion uses a resistor network with
resistance values that represent the binary weights of the input bits of the
digital code.
Figure 6.4 shows a 4-bit DAC of this type. Each of the input resistors will
either have current or have no current, depending on the input voltage
level.
If the input voltage is zero (binary 0), the current is also zero. If the input
voltage is HIGH (binary 1), the amount of current depends on the input
resistor value and is different for each input resistor, as indicated in the
figure.
6

Figure 6.4: A 4-bit DAC with resistive divider

V
I

From the above figure, 0

8R

I1

V
4R

I2

V
V
and I 3
2R
R

Since there is practically no current into the op-amp inverting input, all of
the input currents sum together and go through R f. Since the inverting input
is at 0 volt (virtual ground), the drop across R f is equal to the output
voltage, so Vout= If Rf.
The values of the input resistors are chosen to be inversely proportional to
the binary weights of the corresponding input bits.
The lowest value resistor (R) corresponds to the highest binary-weighted
input (23). The other resistors are multiples of R (2R, 4R, 8R) and
correspond to the binary weights 22, 21, and 20, respectively.
The input currents are also proportional to the binary weights. Thus, the
output voltage is proportional to the sum of the binary weights because the
sum of the input currents is through Rf.

10

11

12

13

Example 6.1
Determine the output of the DAC in figure below if the waveforms
representing a sequence of 4-bit numbers given below are applied to the
inputs. Input D0 is the least significant bit (LSB).

Solution to Example 6.1

First, determine the current for each of the weighted inputs. Since the
inverting input of the op-amp is at 0 Volt and a binary 1 corresponds to +5V,
the current through any of the input resistors is +5V divided by the
resistance value:

I0

5V
0.025mA
200k

I1

5V
0.05mA
100k

I2

5V
0.1mA
50k

I3

5V
0.2mA
25k
10

Almost no current goes into the inverting op-amp input because of its
extremely high impedance.
Therefore, assume that all of the current goes through the feedback
resistor Rf. Since one end of Rf (virtual ground), the drop across Rf
equals the output voltage, which is negative with respect to virtual
ground.
Vout (D0) = (10) ( - 0.025mA ) = - 0.25V
Vout (D1) = (10) ( - 0.05mA ) = - 0.5V
Vout (D2) = (10) ( - 0.1mA ) = - 1V
Vout (D3) = (10) ( - 0.2mA ) = - 2V

11

From the timing diagram figure, the first binary input code is 0000, which
produces an output voltage of 0V. The next input code is 0001, which
produces an output voltage of -0.25V. For this, the output voltage is -0.25V.
The next code is 0010 which produces an output voltage of -0.5V. The next
code is 0011 which produces an output voltage of -0.25V + -0.5V= -0.75V.

12

Each successive binary code increases the output voltage by -0.25V,

so for this particular straight binary sequence on the inputs, the output is a
stair step waveform going from 0V to -3.75V in -0.25V steps.
This is shown in figure below.

9
13

15

16

17

18

19

Binary Ladder
Another method of D/A conversion is binary ladder or R/2R ladder, as
shown in Figure 6.5 for four bits. It overcomes one of the problems in
the resistive divider network DAC in that it requires only two resistor
values.

Figure 6.5: A 4-bit binary ladder

14

Start by assuming that the D3 input is HIGH (+5V) and the others are LOW
(0V). This condition represents the binary number 1000. A circuit
analysis will show that this reduces to the equivalent form shown in
Figure 6.5(a).

Figure 6.5(a)

14
15

Essentially no current goes through the 2R equivalent resistance because

the inverting input is at virtual ground. Thus, all of the current (I= 5V/2R)
through R7 also goes through Rf, and the output voltage is -5V
The operational amplifier keeps the inverting (-) input near zero volts (0V)
because of negative feedback. Therefore all current goes through Rf
rather than into the inverting input.

14
16

Figure 6.5(b) shows the equivalent circuit when the D2 input is at +5V and
the others are at ground. This condition represents 0100. If we thevenize
looking from R8, we get 2.5V in series with R, as shown.
This results in a current through Rf of I = 2.5V/ 2R, which gives an output
voltage of -2.5V. Keep in mind that there is no current into the op-amp
inverting input and that there is no current through the equivalent resistant to
ground because it has 0V across it, due to the virtual ground.

14

Figure 6.5(b)

17

Figure 6.5(c) shows the equivalent circuit when the D1 input is at +5V and
the others are at ground. This condition represents 0010. Again
thevenizing looking from R8, we get 1.25V in series with R as shown. The
results in a current through Rf of I = 1.25V/ 2R, which gives an output
voltage of -1.25V.

Figure 6.5(c)

14
18

In Figure 6.5(d), the equivalent circuit representing the case where D0 is

at +5V and the other inputs are at ground is shown. This condition
represents 0001. Thevenizing from R8 gives an equivalent of 0.625V in
series with R as shown. The resulting current through Rf is I = 0.625V/
2R, which gives an output voltage of -0.625V.

Figure 6.5(d)

Notice that each successively is lower weighted input produces an output

voltage that is halved, so that the output voltage is proportional to the
binary weight of the input bits.
14 19

Analogue To
Digital Converter

ADC
20

An analog-to-digital converter is a special type of encoder. A basic block

diagram of an A/D converter is shown in Figure 6.6. The input is a single
variable voltage.
The voltage in this case varies from 0 to 3V. The output of the A/D
converter is in binary. The A/D converter translates the analog voltage at
the input into a 4-bit binary word.

Figure 6.6: Block diagram of an A/D converter

21

The A/D conversion process is generally more complex and

time-consuming than the D/A process, and many different
methods have been developed and used.
We shall examine several of these methods in detail. Among
them are a digital-ramp method and a successive
approximation method.

22

Digital-ramp A/D Converter

23

25

26

27

28

29

The digital-ramp method of A/D conversion is also known as the stair

step-ramp or the counter method. It employs a DAC and a binary counter
to generate the digital value of an analog input.
Figure 6.7 illustrates the block diagram of this type of converter. It
contains a counter, a DAC, an analog comparator, and a control AND
gate.

Figure 6.7: Block diagram of digital-ramp A/D converter

24

The analog voltage is applied at the left of this figure. The

comparator checks the voltage coming from the D/A
converter. If the analog input voltage at A is greater than the
voltage at input B of the comparator, the clock is allowed to
increase the count of the BCD counter.
The count on the counter increases until the feedback
voltage from the D/A converter greater than the analog input
voltage. At this point, the comparator stops the counter from
advancing to a higher count. Suppose the input analog
voltage is 2V. The counter is reset to binary 0000, and the
counter starts counting again.

24
25

Now, for more detail on the A/D converter in Figure 6.7, let us
assume that there is a logical 1 at point X at the output of the
comparator. Also assume that the BCD counter is at binary
0000. Assume, too, that 0.55V is applied to the analog input.
The 1 at point X enables the AND gate, and the first pulse
from the clock appears at the CLK input of the BCD counter.
The counter advances its count to 0001. The 0001 is
displayed on the lights in the upper right of Figure 6.7. The
0001 is also fed back to the D/A converter.

24
26

A binary 0001 produces 0.2V at the output of the D/A converter. The 0.2V is
fed back to the B input of the comparator. The comparator checks its
inputs. The A input is higher (0.55V as opposed to 0.2V), and so that
comparator puts out a logical 1.
The 1 enable the AND gate, which lets the next clock pulse through to the
counter. The counter advances its count by 1. The count is now 0010. The
0010 is fed back to the D/A converter. The same process will be repeated
for the rest of the input analog voltage.
The counter would have to count from binary 0000 to 0110 before being
stop by the comparator. If the input analog voltage were 2.8V, the binary
output will be 1110 before being stopped by the comparator. Notice that it
does take some time for the conversion of the analog voltage to a binary
readout.
24
27

Figure 6.8 illustrates a conversion sequence for a 4-bit

conversion. Notice that for each sample, the counter must
count from zero up to the point at which the stair step
reference voltage reaches the analog input voltage. The
conversion time varies, depending on the analog voltage.

24

Figure 6.8: The stairstep reference voltage for

a 4-bit digital-ramp ADC

28

Example 6.2
Assume the following values for the digital-ramp ADC:
clock frequency = 1MHz; DAC full-scale output = 1.5V and
a 4-bit input.
Determine the following values.
a.The digital equivalent obtained for VA= 0.78V
b.The conversion time
c.The resolution of this converter

29

Solution to Example 6.2

The DAC has a 4-bit input and a 1.5V full-scale output. Thus, the
number of total possible steps is 24 -1= 15, and so the step size is

1.5V
= 0.1V
15
This means
require are

the

steps

0.78V
= 7.8 8 steps
0.1V

a. At the end of the conversion, then, the counter will hold the binary
equivalent of 8, which is 1000. This is the desired digital equivalent of
VA= 0.78V, as produced by this ADC.

30

b. Eight steps were required to complete the conversion. Thus, 8

clock pulses occurred at the rate of the one per microsecond. This
gives a total conversion time of 8 s.
c. The resolution of this converter is equal to the step size of the DAC,
which is 0.1V. In percent it is 1/15 x 100% 6.67%.

31

Successive Approximation
A/D Converter

32

The successive-approximation converter is one of the most

widely used types of A/D converter. It has more complex
circuitry than the digital ramp A/D converter but a much
shorter conversion time.
In addition, successive approximation converters (SAC) have
a fixed value of conversion time that is not dependent on the
value of the analog input.

33

Figure 6.9 shows a basic block diagram of a 4-bit SAC. It

consists of a DAC, a successive-approximation register
(SAR), and a comparator.

Figure 6.9: A 4-bit SAC A/D converter

34

The basic operation is as follows:

The input bits of the DAC are enabled (made equal to 1) one
at a time, starting with the MSB.
As each bit is enabled, the comparator produces an output that
indicates whether the analog input voltage is greater or less
than the output of the DAC.
If the DAC is greater than the analog input, the comparators
output is LOW, causing the bit of the register to RESET.

35

If the output is less than the analog input, the 1 bit is

retained in the register.
The system does this with the MSB first, then the next
most significant bit, then the next, and so on.
After all the bits of the DAC have been tried, the
conversion cycle is complete

36

Example 6.3
Describe the operation of the 4-bit SAC. Assume
that the constant analog input voltage is +5V.
Lets assume the output characteristics of DAC are:
Vout = 8V for the 23 (MSB), Vout= 4V for the 22 bit,
Vout= 2V for the 21 bit and Vout = 1V for the 20 bit
(LSB).

37

39

40

41

42

Figure
Example 6.3

43

38

Solution to Example 6.3

Figure (a) shows the first step in the conversion cycle
with the MSB = 1.
The output of the DAC is 8V. Since this is greater than
the analog input of 5 V, the output of the comparator is
LOW, causing the MSB in the SAR to be RESET to a
0.

38
39

Figure (b) shows the second step in the conversion

cycle with the 22 bit equal to a 1.
The output of the DAC is 4V. Since this is less than
the analog input of 5 V, the output of the comparator
switches to a HIGH, causing this bit to be retained in
the SAR.

38
40

Figure (c) shows the third step in the conversion

cycle with the 21 bit equal to a 1.
The output of the DAC is 6V because there is a 1 on
the 22 bit input and on the 21 bit input; 4V + 2V = 6V.
Since this is greater than the analog input of 5 V, the
output of the comparator switches to a LOW, causing
this bit to be RESET to a 0.

38
41

Figure (d) shows the fourth and final step in the

conversion cycle with the 20 bit equal to a 1.
The output of the DAC is 5 V because there is a 1
on the 22 bit input and on the 20 bit input; 4V + 1V =
5V.

38
42

The four bits have all been tried, thus completing the
conversion cycle. At this point the binary code in the
register is 0101, which is the binary value of the analog
input of 5V.
Another conversion cycle now begins, and the basic
process is repeated. The SAR is cleared at the beginning of
each cycle.

38
43

44

45

46