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different clocks
or different edges of a clock
but clock periods should be same
ELEN 468 Lecture 14
Commonly Synthesized
Sequential Logic
Data register
Transparent latch
Shift register
Binary counter
Finite state machine
Pulse generator
Clock generator
Parallel/serial converter
Synthesis of Sequential
UDPs
Only one synchronizing signal
Example of Sequential
UDP
primitive d_flop( q, clock, d );
clock
output
q;
input
clock, d;
d
q
d_flop
reg q;
table
// clock d
state q/next_state
(01) 0
: ?
:
0;
// Parentheses indicate signal
transition
(01) 1
: ?
:
1;
// Rising clock edge
(0?) 1
: 1
: 1;
(0?) 0
: 0
: 0;
(?0) ?
:
?
:
-;
// Falling clock edge
?
(??) :
?
:
-;
// Steady clock
endtable
endprimitive
Synthesis of Latches
Latches are incurred at
feedback
Edge-triggered cyclic behavior -> gated
datapath
Level-sensitive cyclic behavior -> latch
Feedback loop
ELEN 468 Lecture 14
b
selA
selB
selA
selB
en
latch
enabl
e
in
mux
out
always
always@
@((enable
enable))
begin
begin
ifif((enable
enable))
assign
assignout
out==in;
in;
else
else
assign
assignout
out==out;
out;
end
end
endmodule
endmodule
10
11
Registered Combinational
Logic
module
modulereg_and
reg_and((y,
y,a,
a,b,
b,c,
c,
clk
clk););
input
inputa,
a,b,
b,c,
c,clk;
clk;
output
outputy;
y;
reg
regy;
y;
always
always@
@((posedge
posedgeclk
clk))
yy==aa&&bb&&c;
c;
endmodule
endmodule
clk
12
Shift Register
module
moduleshift4
shift4((out,
out,in,
in,clock,
clock,reset
reset););
input
inputin,
in,clock,
clock,reset;
reset;
output
outputout;
out;
reg
reg[3:0]
[3:0]data_reg;
data_reg;
assign
assignout
out==data_reg[0];
data_reg[0];
always
always@
@((negedge
negedgereset
resetor
orposedge
posedge
clock
)
clock )
begin
begin
ifif((reset
reset==
==1b0
1b0))data_reg
data_reg==4b0;
4b0;
else
elsedata_reg
data_reg=={{in,
in,data_reg[3:1]
data_reg[3:1]};
};
end
end
endmodule
endmodule
13
Counter
module
moduleripple_counter
ripple_counter((count,
count,clock,
clock,toggle,
toggle,reset
reset););
input
inputclock,
clock,toggle,
toggle,reset;
reset; output
output[3:0]
[3:0]count;
count;
reg
reg[3:0]
[3:0]count;
count; wire
wirec0,
c0,c1,
c1,c2;
c2;
assign
c0
=
count[0];
assign
c1
assign c0 = count[0]; assign c1==count[1];
count[1]; assign
assignc2
c2==
count[2];
count[2];
always
always@
@((posedge
posedgereset
resetor
orposedge
posedgeclock
clock))
ifif((reset
reset==
==1b1
1b1))count[0]
count[0]==1b0;
1b0;
else
elseifif((toggle
toggle==
==1b1
1b1))count[0]
count[0]==~count[0];
~count[0];
always
always@
@((posedge
posedgereset
resetor
ornegedge
negedgec0
c0))
ifif((reset
reset==
==1b1
1b1))count[1]
count[1]==1b0;
1b0;
else
elseifif((toggle
toggle==
==1b1
1b1))count[1]
count[1]==~count[1];
~count[1];
always
always@
@((posedge
posedgereset
resetor
ornegedge
negedgec1
c1))
ifif((reset
reset==
==1b1
1b1))count[2]
count[2]==1b0;
1b0;
else
if
(
toggle
==
1b1
)
count[2]
else if ( toggle == 1b1 ) count[2]==~count[2];
~count[2];
always
@
(
posedge
reset
or
negedge
always @ ( posedge reset or negedgec2
c2))
ifif((reset
reset==
==1b1
1b1))count[3]
count[3]==1b0;
1b0;
else
elseifif((toggle
toggle==
==1b1
1b1))count[3]
count[3]==~count[3];
~count[3];
endmodule
endmodule
Fig. 9.14
Page
366
14
Implicit FSM
Explicit State
Register
Yes
No
State Encoding
Yes
No
Sequence of
States
Specified
Implicit
Sequence
Control
Explicit
assignment to
state register
Specified by
procedural
flow
16
Binary
Gray
Johnson
One-hot
000
000
0000
00000001
001
001
0001
00000010
010
011
0011
00000100
011
010
0111
00001000
100
110
1111
00010000
101
111
1110
00100000
110
101
1100
01000000
111
100
1000
10000000
17
State Encoding
A state machine having N states will
require at least log2N bits register to store
the encoded representation of states
Binary and Gray encoding use the
minimum number of bits for state register
Gray and Johnson code:
Reduce crosstalk
Reduce glitch
18
One-hot Encoding
Employ one bit register for each state
Less combinational logic to decode
Consume greater area, does not matter for
certain hardware such as FPGA
Easier for design, friendly to incremental
change
case and if statement may give different
result for one-hot encoding
define
definestate_0
state_03b001
3b001
Runs faster
define
definestate_1
state_13b010
3b010
define
definestate_2
state_23b100
3b100
19
always
always@
@((posedge
posedgeclock
clock););
begin
begin
aa<=
<=b;
b;
cc<=
<=d;
d;
@(
@(negedge
negedgeclock
clock))
begin
begin
ee<=
<=f;f;
gg<=
<=h;
h;
end
end
end
end
20
Resets
Strongly recommended that every
sequential circuit has a reset signal
Avoid uncertain initial states
Specification for output under reset
should be complete, otherwise
wasted logic might be generated
21
Gated Clock
Pro: reduce power consumption
Con: unintentional skew
dat
a
cloc
k
clock_enabl
e
Q
flipflop
22
Design Partitions
Partition cells such that connections
between partitions is minimum
1
2
3
a
2
c
23
Example: Sequence
Detector
Single bit serial input
Cloc
k
Input
Outpu
t
24
0/0
0/1
State1
Input 0
Start
state
1/0
1/1
1/0
0/0
ELEN 468 Lecture 14
State2
Input 1
25