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Contents
1.
2.
3.
4.
5.
6.
7.
8.
Introduction
Historical Measurements
New Comparison Methodology
FPGA CAD Flow
ASIC CAD Flow
Comparison Metrics
Results
Conclusion
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Introduction
Motivations of the Research
Focus on a Comparison
Historical Measurements
S.D. Brown [1992]
Examined area and delay, but estimated the values for ASIC
Performed only a single module
5
Synthesis: QIS
RTL Design
Description
Synthesis:
QIS
PNR:
Fitter
STA:
Analyzer
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Comparison Metrics
Area
Speed
Power
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Results
Area
Area ratio
The hard heterogeneous
blocks do significantly reduce
area gap.
Heterogeneous blocks are
fundamentally similar to an
ASIC except a programmable
interface.
FPGAs take 40 times more
area than ASICs when only
logic used.
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Results
Speed
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Results
Power
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Conclusion
This paper has presented empirical measurements
quantifying the gap between FPGAs and ASICs.
For logic-only circuits, FPGAs show on average 40
times larger area and 3.2 times slower speed and 12
times more dynamic power consumption than ASICs.
The use of hard multipliers and dedicated memories
enable a substantial reduction in area and power
consumption but have a relatively minor impact on the
delay differences.
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The End
Thank You
Q&A
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