Introduction

Introduction and Basic Concept

What is Verilog?
Hardware Description Language(HDL)

Why use Verilog?

Because 60% of US companies use it.

Why Verilog?
Why use an HDL?
Describe complex designs (millions of gates)
Input to synthesis tools (synthesizable subset)
Design exploration with simulation

Why not use a general purpose language

Support for structure and instantiation

Support for describing bit-level behavior
Support for timing
Support for concurrency

Verilog vs. VHDL

Verilog is relatively simple and close to C
VHDL is complex and close to Ada
Verilog has 60% of the world digital design market (larger share in US)

Why Verilog?

Why Verilog?

Verilog HDL and Verilog-XL

Verilog HDL
Hardware design language that allows you to
design circuit.

Verilog-XL
High speed, event-driven simulator that reads
Verilog HDL and simulates the behavior of
hardware.

Modern Project Methodology

Always
inst1
inst2
inst3

Synthesis

in
p
ap
m

Place and
Route

clb 1
clb 2

Introduction to
Verilog only

Objectives

Understand the design methodologies using Verilog

Target audience
have basic digital circuits design concept
knowledge of VHDL for design of digital systems
Verilog description for logic synthesis

NOT in the talk

a full coverage of Verilog

Contents
Verilog HDL
structured modeling
RTL modeling

Example combinational circuits

structured description (net-list)
RTL

Example sequential circuits

RTL

FSM
combinational circuits
sequential circuits

Verilog history
Gateway Design Automation
Phil Moorby in 1984 and 1985

Verilog-XL, "XL algorithm", 1986

a very efficient method for doing gate-level simulation

Verilog logic synthesizer, Synopsys, 1988

the top-down design methodology is feasible

Cadence Design Systems acquired Gateway

December 1989
a proprietary HDL

Verilog history
Open Verilog International (OVI), 1991
Language Reference Manual (LRM)
making the language specification as vendorindependent as possible.

The IEEE 1364 working group, 1994

to turn the OVI LRM into an IEEE standard.

Verilog became an IEEE standard

December, 1995.

Hardware Description Languages

The functionality of hardware
concurrency
timing controls

The implementation of hardware

structure
net-list

ISP
C. Gordon Bell and Alan Newell at Carnegie Mellon
University, 1972
RTL (register transfer level)

Different Levels of Abstraction

Algorithmic
the function of the system

RTL
the data flow
the control signals
the storage element and clock

Gate
gate-level net-list

Switch
transistor-level net-list

Verilog for Digital System Design

Structural description
net-list using primitive gates and switches
continuous assignment using Verilog operators

RTL
functional description
timing controls and concurrency specification
procedural blocks (always and initial)
registers and latches

C + timing controls + concurrency

Verilog Procedural
Descriptions

Verilog Variables

Tricky Delay

Initial Block

Verilog Usage

Different States

Procedural
Statements

Still a Problem?

Hierarchical structure and

Modules

Represent the hierarchy of a design

modules
the basic building blocks

ports
the I/O pins in hardware
input, output or inout

Event Driven Simulation

Verilog is really a language for modeling event-driven systems
Event : change in state

Event
queue

t t+1

Events

Simulation starts at t = 0
Processing events generates new events
When all events at time t have been processed simulation time advances to t+1
Simulation stops when there are no more events in the queue

Modeling Structure: Modules

The module is the basic building block in Verilog
Modules can be interconnected to describe the structure of your digital system
Modules start with keyword module and end with keyword endmodule

ModuleAND<portlist>

ModuleCPU<portlist>

Moduleshaveportsforinterconnectionwithothermodules
endmodule

endmodule

Modeling Structure: Ports

Module Ports
Similar to pins on a chip
Provide a way to communicate with outside world
Ports can be input, output or inout
ModuleAND(i0,i1,o);
inputi0,i1;
outputo;

i0
o
i1

endmodule

Modeling Structure: Instances

Module instances

Verilog models consist of a hierarchy of module instances

In C++ speak: modules are classes and instances are objects
AND3
i0
i1

i2

ModuleAND3(i0,i1,i2,o);
inputi0,i1,i2;
output0;
wiretemp;
ANDa0(.i0(i0),.i1(i1),.o(temp));
ANDa1(.i0(i2),.i1(temp),.o(0));
endmodule

Logic Values
0: zero, logic low, false, ground
1: one, logic high, power
X: unknown
Z: high impedance, unconnected, tri-state

Data Types
Nets
Nets are physical connections between devices
Nets always reflect the logic value of the driving device
Many types of nets, but all we care about is wire

Registers
Implicit storage unless variable of this type is
modified it retains previously assigned value
Does not necessarily imply a hardware register
Register type is denoted by reg
intis also used

Variable Declaration
Declaring a net
wire[<range>]<net_name>[<net_name>*];
Range is specified as [MSb:LSb]. Default is one bit wide

Declaring a register
reg[<range>]<reg_name>[<reg_name>*];

Declaring memory
reg[<range>]<memory_name>[<start_addr> : <end_addr>];

Examples
regr;//1bitregvariable
wirew1,w2;//21bitwirevariable
reg[7:0]vreg;//8bitregister
reg[7:0]memory[0:1023];a1KBmemory

Ports and Data Types

Correct data types for ports
Module

Register/net

net
input

register/net
output

net
inout
net

net

Structural Modeling
Structural Verilog describes connections of
modules (netlist)
and a0(.i0(a), .i1(b), .o(out));

Modules

The principal design entity

Module Name &
Port List

Definitions
Ports, Wire, Reg,
Parameter

Module Statements &

Constructs

Module
Instatiations

Example
4-bit adder
module add4 (s,c3,ci,a,b)
input [3:0] a,b ; // port declarations
input ci ;
output [3:0] s : // vector
output c3 ;
wire [2:0] co ;
add a0 (co[0], s[0], a[0], b[0], ci) ;
add a1 (co[1], s[1], a[1], b[1], co[0]) ;
add a2 (co[2], s[2], a[2], b[2], co[1]) ;
add a3 (c3, s[3], a[3], b[3], co[2]) ;

endmodule

Simpler than VHDL

Only Syntactical
Difference

c3

a3

a2

a1

a0

ci

Data types
Net

physical wire between devices

the default data type
used in structural modeling and continuous assignment
types of nets
wire, tri
Simpler than VHDL
: default

wor, trior
wand, triand
trireg
tri1
tri0
supply1
supply0

: wire-ORed
: wire-ANDed
: with capacitive storage
: pull high
; pull low
; power
; ground

Only Syntactical
Difference

Verilog Simulator
Circuit
Description

Testfixture

Verilog Simulator

Simulation Result

Sample Design
1-bit full adder

module fadder ( sum, cout, a, b , ci );

// port declaration
output sum, cout;

a
b
ci

sum

input a, b, ci;
reg

sum, cout;

cout

// behavior description
always @( a or b or ci )
begin
sum = a ^ b ^ ci;
cout = ( a&b ) | ( b&ci ) | ( ci&a);
end
endmodule

Simpler than VHDL

Only Syntactical
Difference

Basic
Instructions

Lexical Conventions in
Verilog
Type of lexical tokens :
Operators ( * )
White space
Comment
Number ( * )
String
Identifier
Keyword ( * )

Note : * will be

Reg and Parameters

Reg

variables used in RTL description

a wire, a storage device or a temporary variable
reg
: unsigned integer variables of varying bit width
integer : 32-bit signed integer
real
: signed floating-point
time : 64-bit unsigned integer

Parameters
run-time constants

Special Language Tokens

$<identifier>: System tasks and functions

$time
$stop
$finish
$monitor
$ps_waves
$gr_waves
$gr_regs

#<delay specification>
used in
gate instances and procedural statements
unnecessary in RTL specification

Modeling Structures
Net-list
structural description for the top level

Continuous assignments (combination circuits)

data flow specification for simple combinational
Verilog operators

Procedural blocks (RTL)

always and initial blocks
allow timing control and concurrency

C-like procedure statements

primitives (=truth table, state transition table)

function and task (function and subroutine)

A full-adder
module add (co, s, a, b, c)
input a, b ,c ;
output co, s ;
xor (n1, a, b) ;
xor (s, n1, c) ;
nand (n2, a, b) ;
nand (n3,n1, c) ;
nand (co, n3,n2) ;

endmodule

Simpler than VHDL

Only Syntactical
Difference

Verilog Primitives
Basic logic gates only

and
or
not
buf
xor
nand
nor
xnor
bufif1, bufif0
notif1, notif0

Primitive Pins Are Expandable

One output and variable number of inputs
nand (y, in1, in2) ;

nand (y, in1, in2, in3) ;

nand (y, in1, in2, in3, in4) ;

not and buf

variable number of outputs but only one input

Continuous Assignments
Describe combinational logic
Operands + operators
Drive values to a net

assign out = a&b ; // and gate

assign eq = (a==b) ; // comparator
wire #10 inv = ~in ; // inverter with delay
wire [7:0] c = a+b ; // 8-bit adder

Avoid logic loops

assign a = b + a ;
asynchronous design

Logical and Conditional Operators

Logical, bit-wise and unary operators
a = 1011; b = 0010
logical
bit-wise unary
a || b = 1
a | b = 1011
a && b = 1 a &b = 0010

|a = 1
&a = 0

Conditional operator
assign z = ({s1,s0} == 2'b00) ? IA :
({s1,s0} == 2'b01) ? IB :
({s1,s0} == 2'b10) ? IC :
({s1,s0} == 2'b11) ? ID :
1'bx ;
assign s = (op == ADD) ? a+b : a-b ;

Operators
Arithmetic Operators
Relational Operators
Equality Operators
Logical Operators
Bit-Wise Operators
Unary Reduction
Shift Operators
Conditional Operators
Concatenations

+, -, *, /, %
<, <=, >, >=
==, !=, ===, !==
!, &&, ||
~, &, |, ^, ~^
&, ~&, |, ~|, ^, ~^
>>, <<
?:
{}

Operator Precedence
[ ]
bit-select or partselect
( )
parentheses
!, ~
logical and bit-wise
negation
&, |, ~&, ~|, ^, ~^, ^~
reduction operators
+, unary arithmetic
{ }
concatenation
*, /, % arithmetic
+, arithmetic
<<, >> shift

>, >=, <, <=

relational
==, != logical equality
&
bit-wise AND
^, ^~, ~^
bit-wise XOR and XNOR
|
bit-wise OR
&& logical AND
||
logical OR
?:
conditional

Operators
{}
concatenation
+ - * /
arithmetic
% modulus
> >= < <=
relational
! logical NOT
&& logical AND
|| logical OR
==
logical equality
!= logical inequality
? : conditional

~ bit-wise NOT
& bit-wise AND
| bit-wise OR
^ bit-wise XOR
^~ ~^ bit-wise XNOR
& reduction AND
| reduction OR
~&
reduction NAND
~| reduction NOR
^ reduction XOR
~^ ^~ reduction XNOR
<<
shift left
>>
shift right

Numbers
Format :

<size><base><value>

Example : 8d16
8h10
8b00010000
8o20

Keywords
Note : All keywords are defined in lower case
Examples :
module, endmodule
input, output, inout
reg, integer, real, time
not, and, nand, or, nor, xor
parameter
begin, end
fork, join
specify, endspecify

Value Set in Verilog

4-value logic system in Verilog :
0
X

Major Data Type Class

Nets
Registers
Parameters

Nets
Net data type represent physical
connections between structural
entities.
A net must be driven by a driver,
such as a gate or a continuous
assignment.
Verilog automatically propagates new
values onto a net when the drivers

Registers & Parameters

Registers represent abstract storage
elements.
A register holds its value until a new
value is assigned to it.
Registers are used extensively in
behavior modeling and in applying
stimuli.
Parameters are not variables, they are

Assignments
Assignment : drive values into nets and
registers.
Continuous Assignments Any changes in
the RHS of continuous assignment are
evaluated and the LHS is update.
Example : (1) assign out = ~in;

Assignments ( cont. )
Blocking procedural assignment.
rega = regb + regc;
Non-blocking procedural assignment.
rega <= regb * regc;

RTL
Modeling

RTL Modeling
Describe the system at a high level of abstraction
Specify a set of concurrently active procedural
blocks
procedural blocks = digital circuits

Procedural blocks
initial blocks
test-fixtures to generate test vectors
initial conditions

always blocks
can be combinational circuits
can imply latches or flip-flops

Procedural blocks have the following

components
procedural assignment statements
timing controls
high-level programming language constructs
initial
c
c
statement
c

always
c
c
statement
c

RTL Statements

Procedural and RTL assignments

reg & integer
out = a + b ;

begin . . . end block statements

group statements

if. . . else statements

case statements
for loops
while loops
forever loops
disable statements
disable a named block

Combinational Always Blocks

A complete sensitivity list (inputs)
always @(a or b or c)
f = a&~c | b&c ;

Simulation results
always @(a or b)
f = a&~c | b&c ;

Parentheses
always @(a or b or c or d)
z=a+b+c+d;
// z = (a+b) + (c+d) ;

Sequential Always Blocks

Inferred latches (Incomplete branch specifications)
module infer_latch(D, enable, Q);
input D, enable;
output Q;
reg Q;
always @ (D or enable) begin
if (enable)
Q <= D;
end
endmodule

the Q is not specified in a branch

a latch like 74373

Combinational Circuit Design

Outputs are functions of inputs
inputs

comb.
circuits

Examples

MUX
decoder
priority encoder
adder

Outputs

Multiplexor
Net-list (gate-level)
module mux2_1 (out,a,b,sel) ;
output out ;
input a,b,sel ;
not (sel_, sel) ;
and (a1, a, sel_) ;
and (b1, b, sel) ;
or (out, a1, b1) ;
endmodule

Multiplexor
Continuous assignment
module mux2_1 (out,a,b,sel) ;
output out ;
input a,b,sel ;
assign out = (a&~sel)|(b&sel) ;
endmodule

RTL modeling
always @(a or b or sel)
if(sel)
out = b;

else
out = a;

Multiplexor
4-to-1 multiplexor
module mux4_1 (out, in0, in1, in2, in3, sel) ;
output out ;
input in0,in1,in2,in3 ;
input [1:0] sel ;
assign out = (sel == 2'b00) ? in0 :
(sel == 2'b01) ? in1 :
(sel == 2'b10) ? in2 :
(sel == 2'b11) ? in3 :
1'bx ;
endmodule

Multiplexor
module mux4_1 (out, in, sel) ;
output out ;
input [3:0] in ;
input [1:0] sel ;
reg out ;
always @(sel or in) begin
case(sel)
2d0: out = in[0] ;
2d1: out = in[1] ;
2d2: out = in[2] ;
2d3: out = in[3] ;
default: 1bx ;
endcase
end
endmodule

out = in[sel] ;

Decoder
3-to 8 decoder with an
enable control
module decoder(o,enb_,sel) ;
output [7:0] o ;
input enb_ ;
input [2:0] sel ;
reg [7:0] o ;
always @ (enb_ or sel)
if(enb_)
o = 8'b1111_1111 ;
else

case(sel)
3'b000 : o = 8'b1111_1110 ;
3'b001 : o = 8'b1111_1101 ;
3'b010 : o = 8'b1111_1011 ;
3'b011 : o = 8'b1111_0111 ;
3'b100 : o = 8'b1110_1111 ;
3'b101 : o = 8'b1101_1111 ;
3'b110 : o = 8'b1011_1111 ;
3'b111 : o = 8'b0111_1111 ;
default : o = 8'bx ;
endcase
endmodule

Priority Encoder
always @ (d0 or d1 or d2 or d3)
if (d3 == 1)
{x,y,v} = 3b111 ;

else if (d2 == 1)
{x,y,v} = 3b101 ;

else if (d1 == 1)
{x,y,v} = 3b011 ;

else if (d0 == 1)
{x,y,v} = 3b001 ;

else
{x,y,v} = 3bxx0 ;

Parity Checker
module parity_chk(data, parity);
input [0:7] data;
output parity;
reg parity;

always @ (data)
begin: check_parity
reg partial;
integer n;
partial = data[0];
for ( n = 0; n <= 7; n = n + 1)
begin
partial = partial ^ data[n];
end
parity <= partial;
end
endmodule

Adder
RTL modeling
module adder(c,s,a,b) ;
output c ;
output [7:0] s ;
input [7:0] a,b ;
assign {c,s} = a + b ;
endmodule

Logic synthesis
CLA adder for speed optimization
ripple adder for area optimization

Tri-State
The value z
always @ (sela or a)
if (sela)
out = a ;

else
out = 1bz ;

Another block
always @(selb or b)
if(selb)
out =b ;

else
out = 1bz ;

assign out = (sela)? a: 1bz ;

Registers (Flip-flops) are implied

@(posedge clk) or @(negedge clk)

a positive edge-triggered D flip-flop
always @ (posedge clk)
q=d;

Procedural Assignments
Blocking assignments
always @(posedge clk) begin
rega = data ;
regb = rega ;
end

Non-blocking assignments
always @(posedge clk) begin
regc <= data ;
regd <= regc ;
end

Sequential
Circuit
Design

Sequential Circuit Design

Inputs

Combinational
circuit

Outputs

Memory
elements

a feedback path
the state of the sequential circuits
the state transition

synchronous circuits
asynchronous circuits

Finite State Machine

Moore model
inputs

next
current
comb. state memory state
comb. outputs
circuit
elements
circuit

Mealy model
inputs

next
current
comb. state memory state
comb. outputs
circuit
elements
circuit

Examples

D flip-flop
D latch
register
shifter
counter
pipeline
FSM

Flip-Flop

Synchronous clear

module d_ff (q,d,clk,clr_) ;

output q ;
input d,clk,clr_ ;
reg q ;
always @ (posedge clk)
if (~clr_)
q=0;
else
q=d;
endmodule

Asynchronous clear
always @ (posedge clk or negedge clr_)
if (~clr_)
q=0;
else
q=d;

Register
module register (q,d,clk,clr_, set_) ;
output [7:0] q ;
input [7:0] d ;
input clk,clr_, set_ ;
reg [7:0] q ;
always @ (posedge clk or negedge clr_ or negedge set_)
if (~clr_)
q=0;
else if (~set_)
q = 8b1111_1111 ;
else
q=d;
endmodule

D Latches
D latch
always @ (enable or data)
if (enable)
q = data ;

D latch with gated asynchronous data

always @ (enable or data or gate)
if (enable)
q = data & gate ;

D Latches
D latch with gated enable
always @ (enable or d or gate)
if (enable & gate)
q=d;

D latch with asynchronous reset

always @ (reset or data or gate)
if (reset)
q = 1b0
else if(enable)
q = data ;

Concept of State Machine

Concept of FSM in Verilog

Vending Machine Example

Parity Checker Example

Shifter
module shifter (so,si,d,clk,ld_,clr_) ;
output so ;
input [7:0] d ;
input si,clk,ld_,clr_ ; // asynchronous clear and synchronous load
reg [7:0] q ;
assign so = q[7] ;
always @ (posedge clk or negedge clr_)
if (~clr_)
ld_ d
q=0;
else if (~ld_)
q=d;
si
shifter
else
clk
q[7:0] = {q[6:0],si} ;
endmodule

so

Counter
module bcd_counter(count,ripple_out,clr,clk) ;
output [3:0] count ;
output ripple_out ;
reg [3:0] count ;
input clr,clk ;
wire ripple_out = (count == 4'b1001) ? 0:1 ; // combinational
always @ (posedge clk or posedge clr) // combinational + sequential
if (clr) ;
count = 0 ;
else if (count == 4'b1001)
count = 0 ;
else
count = count + 1 ;
endmodule

Memory
module memory (data, addr, read, write);
input read, write;
input [4:0] addr;
inout [7:0] data;
reg [7:0] data_reg;
reg [7:0] memory [0:8'hff];
parameter load_file = "cput1.txt";
assign data = (read) ? memory [addr] : 8'hz;
always @ (posedge write)
memory[addr] = data;
initial
$readmemb (load_file, memory);
endmodule

Inefficient Description
module count (clock, reset, and_bits, or_bits, xor_bits);
input clock, reset;
output and_bits, or_bits, xor_bits;
reg and_bits, or_bits, xor_bits;
reg [2:0] count;
always @(posedge clock) begin
if (reset)
count = 0;
else
count = count + 1;
and_bits = & count;
or_bits = | count;
xor_bits = ^ count;
end
endmodule

Six implied registers

Efficient Description

Separate combinational and sequential circuits

module count (clock, reset,

and_bits, or_bits, xor_bits);
input clock, reset;
output and_bits, or_bits, xor_bits;
reg and_bits, or_bits, xor_bits;
reg [2:0] count;
always @(posedge clock) begin
if (reset)
count = 0;
else
count = count + 1;
end

// combinational circuits
always @(count) begin
and_bits = & count;
or_bits = | count;
xor_bits = ^ count;
end
endmodule

Three registers are used

Mealy Machine Example

module mealy (in1, in2, clk, reset,out);
input in1, in2, clk, reset;
output out;
reg current_state, next_state, out;
// state flip-flops
always @(posedge clk or negedge
reset)
if (!reset)
current_state = 0;
else
current_state = next_state;
// combinational: next-state and outputs
always @(in1 or in2 or current_state)
case (current_state)

0: begin
next_state = 1;
out = 1'b0;
end
1: if (in1) begin
next_state = 1'b0;
out = in2;
end
else begin
next_state = 1'b1;
out = !in2;
end
endcase
endmodule

Pipelines
comb.
circuits

flipflops

comb.
circuits

flipflops

comb.
circuits

An example
a
b
c

n-sum

Dff

sum
p

Dff

assign n_sum = a+b

assign p = sum * d_c
// plus D flip-flops
always @ (posedge clk)
sum = n_sum ;

d_c

Dff

out

flipflops

A FSM Example
Picture of Highway/Farmroad Intersection:
Farmroad
C

HL

FL

Highway

Highway
HL

Traffic Light Controller

FL
C
Farmroad

Specifications
Traffic Light Controller
? Tabulation of Inputs and Outputs:
Input Signal
reset
C
TS
TL

Description
place FSM in initial state
detect vehicle on farmroad
short time interval expired
long time interval expired

Output Signal
HG, HY, HR
FG, FY, FR
ST

Description
assert green/yellow/red highway lights
assert green/yellow/red farmroad lights
start timing a short or long interval

? Tabulation of Unique States: Some light configuration imply others

State
S0
S1
S2
S3

Description
Highway green (farmroad red)
Highway yellow (farmroad red)
Farmroad green (highway red)
Farmroad yellow (highway red)

The block diagram

C
TS

T
L

Comb.
circuits

n_state

state
FFs

Comb.
circuits

HR
HG
HY
FR
FG
FY

State transition diagram

TL + C
Reset
S0
TLC/ST

S1: HY

TS/ST

TS
S1

S2: FG

S3
TS

TS/ST
S2

TL + C/ST
TL C

S0: HG

S3: FY

Verilog Description
module traffic_light(HG, HY, HR, FG, FY, FR,ST_o,
tl, ts, clk, reset, c) ;
output HG, HY, HR, FG, FY, FR, ST_o;
input tl, ts, clk, reset, c ;
reg ST_o, ST ;
reg[0:1] state, next_state ;
parameter EVEN= 0, ODD=1 ;
parameter S0= 2'b00, S1=2'b01, S2=2'b10, S3=2'b11;
assign HG = (state == S0) ;
assign HY = (state == S1) ;
assign HR = ((state == S2)||(state == S3)) ;
assign FG = (state == S2) ;
assign FY = (state == S3) ;
assign FR = ((state == S0)||(state == S1)) ;

// flip-flops
always@ (posedge clk or posedge reset)
if(reset)
// an asynchronous reset
begin
state = S0 ;
ST_o = 0 ;
end
else
begin
state = next_state ;
ST_o = ST ;
end

always@ (state or c or tl or ts)

case(state) // state transition
S0:
if(tl & c)
begin
next_state = S1 ;
ST = 1 ;
end
else
begin
next_state = S0 ;
ST = 0 ;
end

TL + C
Reset
S0
TLC/ST

TS/ST

TS
S1

S3
TS

TS/ST
S2

TL + C/ST
TL C

S1:
if (ts) begin
next_state = S2 ;
ST = 1 ;
end
else begin
next_state = S1 ;
ST = 0 ;
end
S2:
if(tl | !c) begin
next_state = S3 ;
ST = 1 ;
end
else begin
next_state = S2 ;
ST = 0 ;
end

TL + C
Reset
S0
TLC/ST

TS/ST

TS
S1

S3
TS

TS/ST
S2

TL + C/ST
TL C

S3:
if(ts)
begin
next_state = S0 ;
ST = 1 ;
end
else
begin
next_state = S3 ;
ST = 0 ;
end
endcase
endmodule

TL + C
Reset
S0
TLC/ST

TS/ST

TS
S1

S3
TS

TS/ST
S2

TL + C/ST
TL C

Efficient Modeling
Techniques
Separate combinational and sequential
circuits
always know your target circuits

Separate structured circuits and random logic

structured: data path, XORs, MUXs
random logic: control logic, decoder, encoder

Use parentheses control complex structure

.....

VERILOG Coding Styles

Synthesizable
Behavioral
Register Transfer Level (RTL)
Structural

Behavioral
modeling

Conditional Instructions
if (<condition>)
<statement1>
else
<statement2>

if (a[2:0]==3b010 && cy)

...
case (ir[7:4])
4b0001: ...
4b0010: ...
default: ...
endcase;

case (<expression>)
expr1:
<statement1>;
expr2:
<statement2>;
default: <statement3>;
endcase;

casez

(Z considered dont care)

casex

(Z and X considered dont care)

(expression)?(true):(false)

casex (ir[7:4])
4bxx01: ...
4bxx10: ...
default: ...
endcase;

acc=(ir[7:0]==4b0011) ?
0:255;

Loops
for (<start>;<end_exp>;<update>)
<statement>;

for (i=0;i<8;i=i+1)
...

while (<condition>)
<statement>;

while (i<8)
...

repeat (<loop_count>)
<statement>;

repeat (10)
begin
a[i]=a[i+1];
i=i+1;
end;

forever <statement>;

forever
a = b;

Subroutines
task multiply
input [15:0] a, b;
output [31:0] prod;
begin
...
function [1:0] testDF;
end
input [1:0] Duab, Dvab;
endtask
begin
...
testDF=2b01;
end
endfunction

Modeling Behavior
Behavioral Modeling
Describes functionality of a module

Module Behavior
Collection of concurrent processes
1. Continuous assignments
2. Initial blocks
3. Always blocks

Behavior: Verilog Operators

Arithmetic: +, = , *, /, %
Binary bitwise: ~, &, |, ^, ~^
Unary reduction: &, ~&, |, ~|, ^, ~^
Logical: !, &&, ||, ==, ===, !=, !==
== returns x if any of the input bits is x or z
=== compares xs and zs
Relational: <. >, <=, >+
Logical shift: >>, <<
Conditional: ?:
Concatenation: {}

Behavior:Continuous Assignment
Modulehalf_adder(x,y,s,c)
inputx,y;
outputs,c;
assigns=x^y;
assignc=x&y;
endmodule

Moduleadder_4(a,b,ci,s,co)
input[3:0]a,b;
inputci;
output[3:0]s;
outputco;
assign{co,s}=a+b+ci;
endmodule

Continually drive
wire variables
Used to model
combinational logic
or make
connections
between wires

Behavior: Initial and Always

Multiple statements per block
Procedural assignments
Timing control

Initial blocks execute once

at t = 0
Always blocks execute continuously

at t = 0 and repeatedly thereafter

initial
begin

always
begin

end

end

Behavior: Procedural assignments

Blocking assignment =
Regular assignment inside procedural block
Assignment takes place immediately
LHS must be a register
always
begin
A=B;
B=A;
end

A = B, B= B

Nonblocking assignment <=

Compute RHS
Assignment takes place at end of block
LHS must be a register
always
begin
A<=B;
B<=A;
end

swap A and B

Behavior:Timing Control

Delay #
Used to delay statement by specified amount of simulation time
always
begin
#10clk=1;
#10clk=0;
end

Event Control @
Delay execution until event occurs
Event may be single signal/expression change
Multiple events linked by or
always@(posedgeclk)
begin
q<=d;
end

always@(xory)
begin
s=x^y;
c=x&y;;
end

Behavior: Conditional statements

If,IfElse
if(branch_flg)
begin
PC=PCbr;
end
else
PC=PC+4;

Case
case(opcode)
6b001010:read_mem=1;
6b100011:alu_add=1;
default:
begin
$display(Unknownopcode%h,opcode);
Could also use casez end
(treats z as dont cares ) and casex ( treats z and x as dont cares)
endcase

Behavior: Loop Statements

Repeat

i=0;
repeat(10)
begin
i=i+1;
$display(i=%d,i);
end

While

For

i=0;
while(i<10)
begin
i=i+1;
$display(i=%d,i);
end

for(i=0;i<10;i=i+1)
begin
i=i+1;
$display(i=%d,i);
end

Verilog Coding Rules

Coding rules eliminate strange simulation behavior
When modeling sequential logic, use nonblocking assignments
When modeling combinational logic with always block, use blocking
assignments. Make sure all RHS variables in block appear in @ expression
If you mix sequential and combinational logic within the same always block
use nonblocking assignments
Dont mix blocking and nonblocking assignments in the same always block
Dont make assignments to same variable from more than one always block
Dont make assignments using #0 delays

Verilog Coding Rules: Sequential

Blocks
always@(posedgeclk)
begin
q=d;
end

always@(posedgeclk)
begin
q<=d;
end

always@(posedgeclk)
begin
q1=q;
end

always@(posedgeclk)
begin
q1<=q;
end

RIGHT

WRONG

clk

q1

183 Verilog Synthesizable

coding rules
-

Always keep in mind what sort of implementation your design could map to. If
you dont know, chances are synthesis doesnt either.
The only allowed storage is instantiated dff
-

No loops
No initial blocks
Limited operators
-

No always @ posedge statements

No case statements without default case
No if statements without an else case
If you assign to a net in one case it must be assigned to in all cases (no implicit storage)

+ and are the only arithmetic operators allowed

Try to avoid relational operators (>, ==) in favor of simpler logic

Use assign statements when possible

System and Compiler

System tasks

$time - returns the current simulation time

$display - similar to printf in C
$stop - stops simultion
$finish - ends simulation
$readmemh - load memory array from text file in hex format
Many more

Compiler directives

A compiler directive is preceded by`

`define- defines a compiler time constant or macro
`ifdef,`else,`endif- conditional compilation
`include- text inclusion

Verilog
Example: ASM
Chart

id le

in p u t

s1

in p u t

s2

Want to match pattern

1011

in p u t

s3

in p u t

s3
o u tp u t
1

in p u t

Verilog Example (cont)

module sequence (dataIn, found, clock, reset);
//Input and Output Declarations
input
dataIn;
input
clock;
input
reset;
output
found;
reg
found;
//DataInternal
reg [3:0]
reg [3:0]
wire

Variables
state;
next_state;
found_comb;

//State Declarations
parameter idle = 4'b0001;
parameter s1
= 4'b0010;
parameter s2
= 4'b0100;
parameter s3
= 4'b1000;

Verilog
Example

//Next State Logic

always @(state or dataIn)
case (state)
idle:
if (dataIn)
next_state = s1;
else
next_state = idle;
s1:
if (dataIn)
next_state = s1;
else
next_state = s2;
s2:
if (dataIn)
next_state = s3;
else
next_state = idle;
s3:
if (dataIn)
next_state = s1;
else
next_state = s2;
default:
next_state = idle;
endcase // case(state)

Verilog
Example

//State Transition
always @(posedge clock)
if (reset == 1)
state <= idle;
else
state <= next_state;
//Output Logic
assign found_comb = (state[3] & dataIn);
//Register Output Logic
always @(posedge clock)
if (reset == 1)
found <= 0;
else
found <= found_comb;
endmodule // sequence

Verilog Example :
Simulation

Verilog Example: Synthesis

Top Level

Technology view (Altera 10K)

Verilog Example Xilinx Foundation

Verilog Example Xilinx Foundation

Binary Multiplier Example

n-1

IN
multiplicand

Counter P

Register B

Cout

Adder

multiplier
0

Shift register A

Shift register Q

product
OUT

Behavioral modeling
Learning behavioral modeling by exploring some examples
module DFF ( Din, Dout, Clock, Reset );
output Dout;
input Din, Clock, Reset;
reg

Dout;

always @( negedge Reset or posedge

Clock )
begin
if ( !Reset )

Din

Clock

Dout

DF
F

Dout <= 1b0;

else
Dout <= Din;
end

Reset

Behavioral modeling ( cont. )

module MUX4_1 ( out, i0, i1, i2, i3, sel );
output [3:0] out;
input [3:0] i0, i1, i2, i3;
input [1:0] sel;
assign out = ( sel == 2b00 ) ? i0 :
( sel == 2b01 ) ? i1 :
( sel == 2b10 ) ? i2 :
( sel == 2b11 ) ? i3 :
4bx;
endmodule

2
sel
i0
i1

MUX

i2
i3

out
4

Behavioral modeling ( cont. )

`define pass_accum 4b0000
`define pass_data

4b0001

`define ADD

4b0010

always@ ( opcode ) begin

case ( opcode )
`pass_accum : alu_out <= accum;
`pass_data

: alu_out <= data;

`ADD

: alu_out <= accum + data;

`AND

: alu_out <= accum ^ data;

default

: alu_out <= 8bx;

endcase
end

Module Instantiation
module Top ( Data0, Data1,
Data2,
out0, out1 );
input Data0, Data1, Data2;
output out0, out1;

Top
Data0
Data1

i0
i1

A_to_
out
a0
B

b0

a1

b1

Data2

wire A_to_B;
A a1 ( .i0( Data0 ), .i1( Data1 ),
.out( A_to_B ) );
B b1 ( .a0( A_to_B ), .a1( Data2
),
.b0( out0 ), .b1( out1 ) );
endmodule

Port
mapping

out0

out1

 Verilog:
wire Valid = VL1 & !Illegal;
wire Valid2Sched = !SchedFreeze_ & (Valid_D | Valid);
wire [16:0] LinkIdOMaskL1 = 1'b1 << LinkIdL1;

netlist:
not(n1, Illegal)
and(n2, n1, VL1)
...

Synthesizable Verilog #3 FSMs

parameter IDLE=0, SET_HOURS=1, SET_MINUTES=2;
reg [1:0] CURRENT_STATE, NEXT_STATE; // State
reg HOURS, MINS; // Outputs
always @ (CURRENT_STATE or ALARM_BUTTON or HOURS_BUTTON or
MINUTES_BUTTON) // ADD Clock for synchronous FSM
begin
HOURS = 0; MINS = 0; NEXT_STATE = CURRENT_STATE;
case (CURRENT_STATE) //synopsys full_case parallel_case
IDLE: begin
if (ALARM_BUTTON & HOURS_BUTTON & !MINUTES_BUTTON)
begin
NEXT_STATE = SET_HOURS;
HOURS = 1;
end
else if (ALARM_BUTTON & !HOURS_BUTTON &
MINUTES_BUTTON)
...

modules
module
module RegLd(Q,
RegLd(Q, D,
D,
load,
load, clk);
clk);
parameter
parameter NN == 8;
8;
input
input [N-1:0]
[N-1:0] Q;
Q;
output
output [N-1:0]
[N-1:0] D;
D;
input
input load,
load, Clk;
Clk;
always
always @(posedge
@(posedge clk)
clk)
if
if (load)
(load)
QQ == #`dh
#`dh D;
D;
endmodule
endmodule

RegLd
RegLd

reg0(q0,
reg0(q0, d0,
d0, l,
l, clk);
clk);

RegLd
RegLd #16
#16 reg1(q1,
reg1(q1, d1,
d1, l,
l, clk);
clk);
RegLd
reg2(q2,
RegLd
reg2(q2, d2,
d2, l,
l, clk);
clk);
defparam
defparam reg2.N
reg2.N == 4;
4;

Sensitivity lists
always
always @(posedge
@(posedge clk
clk or
or negedge
negedge rst_)
rst_)
...
...
always
always @(a
@(a or
or bb or
or c)
c)
if
(opcode
==
32h52A0234E)
if (opcode == 32h52A0234E)
aa == bb ^^ (~c);
(~c);
always
always @(posedge
@(posedge aa or
or posedge
posedge b)
b)
...
...

Behavioral (1)
simulation

Test benches

initial
initial begin
begin
//
// reset
reset everything
everything
end
end
always
always @(posedge
@(posedge clk)
clk) begin
begin
case
case (opcode)
(opcode)
8hAB:
8hAB: RegFile[dst]
RegFile[dst] == #2
#2 in;
in;
8hEF:
8hEF: dst
dst == #2
#2 in0
in0 ++ in1;
in1;
8h02:
8h02: Memory[addr]
Memory[addr] == #2
#2 data;
data;
endcase
endcase
if
if (branch)
(branch)
dst
dst == #2
#2 br_addr;
br_addr;
end
end

Behavioral (2)
integer
integer sum,
sum, i;
i;
integer
integer opcodes
opcodes [31:0];
[31:0];
real
real average;
average;
initial
initial
for
for (i=0;
(i=0; i<32;
i<32; i=i+1)
i=i+1)
opcodes[i]
opcodes[i] == 0;
0;

always
always @(posedge
@(posedge clk)
clk) begin
begin
sum
sum == sum
sum ++ 1;
1;
average
average == average
average ++ (c
(c // sum);
sum);
opcodes[d]
opcodes[d] == sum;
sum;
$display(sum:
$display(sum: %d,
%d, avg:
avg: %f,
%f,
sum,
sum, average);
average);
end
end

Verification of Design

Differences
between Tasks
and Functions

Tasks versus Functions in

Verilog
Procedures/Subroutines/Functions in SW
programming languages
The same functionality, in different places

Verilog equivalence:
Tasks and Functions
Used in behavioral modeling
Part of design hierarchy Hierarchical name

Differences between...
Functions
Can enable (call) just
another function (not task)
Execute in 0 simulation time
No timing control statements
allowed
At lease one input
Return only a single value

Tasks
Can enable other tasks and
functions
May execute in non-zero
simulation time
May contain any timing
control statements
May have arbitrary input,
output, or inouts
Do not return any value

Differences between (contd)

Both

are defined in a module

are local to the module
can have local variables (registers, but not nets) and events
contain only behavioral statements
do not contain initial or always statements
are called from initial or always statements or other tasks or
functions

Differences between (contd)

Tasks can be used for common Verilog code
Function are used when the common code
is purely combinational
executes in 0 simulation time
provides exactly one output

Functions are typically used for conversions and

commonly used calculations

Tasks

Tasks
Keywords: task, endtask
Must be used if the procedure has
any timing control constructs
zero or more than one output arguments
no input arguments

Tasks (contd)
Task declaration and invocation
Declaration syntax
task <task_name>;
<I/O declarations>
<variable and event declarations>
begin // if more than one statement needed
<statement(s)>
end
// if begin used!
endtask

Tasks (contd)
Task declaration and invocation
Task invocation syntax
<task_name>;
<task_name> (<arguments>);

input and inout arguments are passed into the task

output and inout arguments are passed back to the
invoking statement when task is completed

Tasks (contd)
I/O declaration in modules vs. tasks
Both used keywords: input, output, inout
In modules, represent ports
connect to external signals

In tasks, represent arguments

pass values to and from the task

Task Examples
Use of input and output arguments
module operation;
parameter delay = 10;
reg [15:0] A, B;
reg [15:0] AB_AND, AB_OR, AB_XOR;
initial
$monitor( );
initial
begin

end
always @(A or B)
begin
bitwise_oper(AB_AND, AB_OR,
AB_XOR, A, B);
end

task bitwise_oper;
output [15:0] ab_and, ab_or,
ab_xor;
input [15:0] a, b;
begin
#delay ab_and = a & b;
ab_or = a | b;
ab_xor = a ^ b;
end
endtask

endmodule

Task Examples
Use of module local variables
module sequence;
reg clock;
initial
begin

end
initial
init_sequence;
always
asymmetric_sequence;

task init_sequence;
begin
clock = 1'b0;
end
endtask
task asymmetric_sequence;
begin
#12 clock = 1'b0;
#5 clock = 1'b1;
#3 clock = 1'b0;
#10 clock = 1'b1;
end
endtask
endmodule

Functions

Functions
Keyword: function, endfunction
Can be used if the procedure
does not have any timing control constructs
returns exactly a single value
has at least one input argument

Functions (contd)
Function Declaration and Invocation
Declaration syntax:
function <range_or_type> <func_name>;
<input declaration(s)>
<variable_declaration(s)>
begin // if more than one statement needed
<statements>
end // if begin used
endfunction

Functions (contd)
Function Declaration and Invocation
Invocation syntax:
<func_name> (<argument(s)>);

Functions (contd)
Semantics
much like function in Pascal
An internal implicit reg is declared inside the function
with the same name
The return value is specified by setting that implicit reg
<range_or_type> defines width and type of the implicit
reg
type can be integer or real
default bit width is 1

Function Examples
Parity Generator
module parity;
reg [31:0] addr;
reg parity;
Initial begin

end

function calc_parity;
input [31:0] address;
begin
calc_parity = ^address;
end
endfunction
endmodule

always @(addr)
begin
parity = calc_parity(addr);
$display("Parity calculated = %b",
calc_parity(addr) );
end

Function Examples
Controllable Shifter
module shifter;
`define LEFT_SHIFT
1'b0
`define RIGHT_SHIFT
1'b1
reg [31:0] addr, left_addr,
right_addr;
reg control;
initial
begin

end
always @(addr)begin
left_addr =shift(addr, `LEFT_SHIFT);
right_addr =shift(addr,`RIGHT_SHIFT);
end

function [31:0] shift;

input [31:0] address;
input control;
begin
shift = (control==`LEFT_SHIFT) ?
(address<<1) : (address>>1);
end
endfunction
endmodule

Tasks and Functions Summary

Tasks and functions in behavioral modeling

The same purpose as subroutines in SW

Provide more readability, easier code management
Are part of design hierarchy
Tasks are more general than functions
Can represent almost any common Verilog code

Functions can only model purely combinational

calculations

Chap 5.
Arithmetic Functions and
Circuits
Spring 2004
Jong Won Park
jwpark@crow.cnu.ac.kr

5-1 Iterative Combinational Circuits

Figure 5-1
Block Diagram of an Iterative Circuit

5-2 Binary Adders

Arithmetic Circuit
a combinational circuit for arithmetic operations
such as addition, subtraction, multiplication, and
division
S = X'Y + XY' = X Y;
C = XY
with binary numbers or decimal numbers
in a binary
code

Addition of 2 binary inputs, 'Half Adder

Table 5-1
Figure 5-2 Logic Diagram
0+0=0,
0+1=1,
1+1 = 10of Half Adder
Truth Table
of Half 1+0=1,
Adder

5-2 Binary Adders

Addition of 3 binary inputs, 'Full Adder'

Table 5-2
Truth Table of Full Adder

Figure 5-3 Logic Diagram of Half Adder

Figure 5-4
Logic Diagram
of Full Adder

5-2 Binary Adders

Binary Ripple Carry Adder
sum of two n-bit binary numbers in parallel
4-bit parallel adder
A = 1011, B = 0011

Figure 5-5 4-Bit Ripple Carry Adder

5-2 Binary Adders

Carry Lookahead Adder
The ripple carry adder has a long circuit delay
the longest delay: 2 n + 2 gate delay
Carry Lookahead Adder
reduced delay at the price of complex hardware

a new logic hierarchy

Pi: propagate function
Gi: generate function

5-2 Binary Adders

Figure 5-6
Development of
a Carry Lookahead
Adder

5-3 Binary Subtraction

Subtraction

a borrow occurs into the most significant position

M - N ==> M - N + 2n
==> 2n - (M - N + 2n) = N - M

1) Subtract the subtrahend N from the minuend M

2) If no end borrow occurs, then M > N
3) If an end borrow occurs,
then N-M is subtracted from 2n
& minus sign is appended to the result

Subtraction of a binary number from 2n

"2's complement form"

10 end borrow
63
-72
-------91 100-91
-9

5-3 Binary Subtraction

Ex 5-1) 01100100 - 10010110

Figure 5-7
Block Diagram of Binary
Adder-Subtracter

5-3 Binary Subtraction

Complements
2 types:
radix complement: r's complement
diminished radix complement: (r-1)'s complement
2's & 1's for binary numbers
10's & 9's for decimal numbers

1's complement of N (binary number): (2n - 1) - N

1's comp of 1011001 ==> 0100110
1's comp of 0001111 ==> 1110000

5-3 Binary Subtraction

2's complement of N: 2n - N for N != 0, 0 for N = 0
1) add 1 to the 1's complement
2's comp of 101100 ==> 010011 + 1 ==> 010100
2) leaving all least significant 0's and the first 1 unchanged then
replacing 1's with 0's, 0's with 1's
2's comp of 1101100 ==> 0010100
2's complement of N is 2n N
& the complement of the complement is 2n - (2n-N) = N

5-3 Binary Subtraction

Subtraction with
Complements
(M - N)
1) add 2's comp of the
subtrahend N to the minuend
M
M + (2n-N) = M - N + 2n
2) if M > N, the end cary is
discarded
3) if M < N, the result is 2n (N - M)
take the 2's complement of
the sum & place a minus sign
avoid overflow problem to
accommodate the sum

Ex 5-2) X=1010100 Y=1000011

5-4 Binary Adder-Subtractors

Figure 5-8 Adder-Subtractor Circuit

A - B = A + (-B) in 2's complement form

with exclusive-OR gate (B0=B; B1=B')
adder if S = 0; subtractor if S = 1

5-4 Binary Adder-Subtractors

Signed Binary Numbers
sign bit: 0 for positive numbers
1 for negative numbers
-9 (=-1001) using 8 bits

1) signed-magnitude representation:

10001001

2) signed 1's complement representation: 1111 0110

3) signed 2's complement representation: 1111 0111
positive numbers are identical(Table 5-3)

signed-magnitude -7 ~ -1, -0, 0, 1 ~ 7 (2 zeros)

signed 1's comp

-7 ~ -1, -0, 0, 1 ~ 7 (2 zeros)

signed 2's comp

-8 ~ -1, 0, 1 ~ 7

signed 1's comp : useful as a logical operation

signed 2's comp : popular in use

5-4 Binary Adder-Subtractors

Table 5-3
Signed Binary Numbers

5-4 Binary Adder-Subtractors

Ex 5-4)Binary
Signed Binary
Adding
2s Complement
Signed
Addition
andUsing
Subtraction

Ex 5-5) Signed Binary Subtraction Using 2s Complement

5-4 Binary Adder-Subtractors

Overflow
8-bit data(1-bit sign): -27 ~ +(27-1) = -128 ~ +127

Figure 5-9 Overflow Detection Logic for Addition and Subtraction

5-5 Binary Multipliers

a 2-Bit by 2-Bit Binary
Multiplier

Figure 5-10 A 2-Bit by 2-Bit Binary Multiplier

5-5 Binary Multipliers

a 4-Bit by 3-Bit Binary Multiplier

Figure 5-11 A 4-Bit by 3-Bit Binary Multiplier

5-6 Other Arithmetic Functions

Contraction
making a simpler circuit for a specific application
Ex 5-6) Contraction of Full Adder Equations

5-6 Other Arithmetic Functions

Ex 5-6) Contraction of Full Adder Equations
S = A + B + C0 S = A + 111 + C0
= A - 1 + C0 (in 2s complement)
if C0 = 0, S is a decrement of A
Incrementing
adding a fixed value(ex, 1) to an arithmetic variable
N-bit incrementer
S = A + 1 from S = A + B + C0 by setting B to 00..01 and
C0 to 0

5-6 Other Arithmetic Functions

Incrementing( 0 , X because of 3-bit incrementer)

Figure 5-12 Contraction of Adder to Incrementer

5-6 Other Arithmetic Functions

Multiplication by
Constants

Figure 5-13 Contractions of

Multiplier
(a) For 101 X B
(b) For 100 X B, and
(c) For B / 100

5-7 HDL Representations-VHDL

Ex 5-7)Hierarchical
VHDL for
a 4 Bit Ripple Carry
Adder
V C(3) XOR
C4
Figure 5-14 Hierarchical
Structure/Dataflow Description
Of 4-Bit Full Adder

5-7 HDL Representations

Figure 5-15 Hierarchical

Structure/Dataflow Description
Of 4-Bit Full Adder(continued)

5-7 HDL Representations

Ex 5-8) Behavioral VHDL for a 4 Bit Ripple Carry
Adder

Figure 5-16 Behavioral Description of 4 bit Full Adder

5-8 HDL Representations-Velilog

Figure 5-17 Hierarchical Dataflow/Structure Description of 4 bit Full Adder

5-8 HDL Representations-Velilog

Ex 5-10) Behavioral VHDL for a 4 Bit Ripple Carry Adder

Figure 5-18 Behavioral Description of 4 bit Full Adder Using Verilog