Memory Interface

Every microprocessor based system has

some memory.
All most all systems contain two types of
memory: Read Only Memory (ROM) and
Random Access Memory (RAM).
There are four common types of memory.
Read Only Memory (ROM), Flash Memory
(EEPROM), Static Random Access Memory
(SRAM), and Dynamic Random Access
Memory (RAM).

 Types of Memories:
Random vs. sequential
Random-Access Memory: each word is
accessible separately equal access time
Sequential-Access Memory: Information stored
is not immediately accessible but only at certain
intervals of time
magnetic disk or tape
access time is variable
Volatile vs. non-volatile
volatile: stored information is lost when power is
turned off
Non-volatile: remains even after power is turned
off
magnetic disk, flash memory

 Static vs. dynamic

SRAM: consists essentially of internal
latches and remains valid as long as power
is applied to the unit
advantage: shorter read and write cycles
DRAM: In the form of electric charges on
capacitors which are provided inside the
chip by MOS transistors
Drawback: Tend to discharge with time and
must be periodically recharged by refreshing,
cycling through the words every few ms.
advantage: reduced power consumption
and larger storage capacity

 Memory Pin Connections:

Pin connections common to all memory devices are the
address inputs, data outputs or input/outputs, some type of
selection input and at least one control input used to select a
read or write operation.
The figure below is for a ROM and RAM devices,

 Address Connections: All memory devices have

address inputs that select a memory location within
the memory device.
Most of the common memory devices have
between 1K to 16M memory locations.
Even 256M memory location devices are also
available.
1K memory devices have 10 address pins (A0-A9);
Means 10 address pins are required to select any
one of the 1024 memory locations.
Similarly, 11 pins for 2K locations

12 pins for 4K locations etc.,

A device containing 1M locations requires 20 bit
address (A0-A19).

 400H represents a 1K- byte of memory section.

If a memory device is decoded to begin at memory
address 10000H, and is 1K device, its last location
is at address 103FF.
A memory device is containing a starting address of
14000H and it is having 4K locations then its last
address is 14FFF
i.e., one less than 1000H
64K is equal to 10000H, If a memory starts at
30000H and is 64K then its last address is 3FFFFH.
1M memory contains 100000H memory locations.
00000 to FFFFF is 1M locations.

 Data Connections: All memory devices have a set

of data outputs or input/outputs.
Data connections are the points at which data are
entered for storage or extracted for reading.
Data pins are labeled as D0 through D7 for an 8bit wide memory device.
If a memory device is having 8 I/O connections, it
can store 8 bits of data in each memory location.
An 8-bit wide memory is often called a byte- wide
memory.
Catalog listings for memory devices often refer to
memory locations times bits per memory location.
Example:
1K X 8

 Selection Connections:
Each memory device has an input sometimes
more than one that selects or enables the
memory device.
Chip Select (CS), Chip Enable (CE), or
simply (S) input.
Logic 0 enables and logic 1 disables the
memory device.
If more than one CS connection is present
all must be activated to read or to write.

 Control Connections: All memory devices have

some form of control input or inputs.
A ROM usually has only one control input, while
RAM often has one or two inputs.
The control input most often found on ROM is the
output enable (OE) or gate (G) connection, which
allows data to flow out of the output data pins of the
ROM.
The OE connection enables and disable a set of
three state buffers located within the memory device
and must be active to read data.
A RAM memory device has either one or two control
inputs. If there is one control input, it is often called
R/ W.
This pin selects a read or write operation only if the
device is selected

 ROM Memory: ROM is available in many

forms; EPROM, PROM, EAROM etc.,
2716 is 2Kx8 EPROM

Having 11 Address inputs

8 data outputs
1 CS line
The access time is measured from the appearance of the
address at the address inputs until the appearance of the
data at the output connections

 Static RAM (SRAM) Devices:

Retain data as long as power is applied.
As no special action is required to retain
stored data except power, these devices are
called as Static memory.
4016 is a representative device for all
SRAMs
Having 2KX8 read/write memory.
Having 11 address inputs and 8 data
input/outputs.

 Dynamic RAM (DRAM) Memory:

The largest static RAM available today is a 128x8.
DRAMs are available in much larger size upto
16Mx1.
DRAM is same as SRAM, except it retains data
only for 2 or 4 ms.
So, after 2 or 4 ms it has to be rewritten (refreshed)
because the capacitors which store a logic 1 or
logic 0 lose their charge.
TMS4464 is DRAM which stores 256 K bits of data.
DRAM memory is usually placed on small circuit
boards called Single In-line Memory Modules
(SIMM).

 Address Decoding:
In order to attach a memory device to the microprocessor, it
is necessary to decode the address from the microprocessor
to make the memory function at a unique section or partition
of the memory map.
Without an address decoder, only one memory device can be
connected to a microprocessor, which would make it virtually
useless.
Why Decode memory ?
When the 8086/8088 is compared to the 2716 EPROM, a
difference in number of address connections EPROM is
having 11 and Microprocessor is having 20.
Means, the microprocessor sends out 20-bit address
So, there is mismatch. This mismatch is corrected by the
address decoders.

 Simple NAND Gate Decoder:

When 2Kx8 EPROM is used, address connections A10-A0 0f
the microprocessor are connected to address inputs A10-A0
of EPROM.
The remaining address pins (A19-A11) are connected to the
inputs of a NAND gate decoder

 In this circuit, a single NAND gate decodes the memory

address.
The output of NAND gate is a logic 0 whenever the address
inputs A19-A11 are all logic 1s.
The active low, logic 0 output of the NAND gate decoder is
connected to the CE bar input, which selects the EPROM.
Example:
A A A A A A A A A A A A A A A A A A A A
1 1 1 1 1 1 1 1 1 x x x x x x x x x x x
or
1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
=FF800H
To
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
=FFFFFH
19

18

17

16

15

14

13

12

11

10

 Although this example serves to illustrate decoding, NAND

gates are rarely used to decode memory because each
memory device requires its own NAND gate decoder.
The 3- to- 8 line Decoder: 74LS138
Most commonly found decoder

 The truth table shows only one of the 8 outputs

ever goes low at any time.
Once the 74LS138 is enabled, the address inputs
(C,B and A) select which output pin goes low.
This decoder provides 8 EPROM CE outputs.
It is very powerful device, because it selects 8
different memory devices at the same time.
A Sample decoder: eight 2764 EPROM memory
devices are connected to the decoder
The decoder selects eight 8K bytes blocks of
memory for a total of 64K bytes of memory.

Figure : A circuit that uses eight 2764 EPROM for a 64K X 8 section of
memory in an 8086 microprocessor based system. The addresses
selected in this circuit are F0000H-FFFFFH

 All the address connections of 8088/8086 are connected.

The CE bar inputs of EPROMs are connected to the eight
outputs of the decoder
RD bar signal from the microprocessor is connected to the
OE bar inputs of the EPROMs.
This allows only the selected EPROM to be enabled and to
send its data to the microprocessor through the data bus
whenever Rd bar is 0
In this circuit a 3-input NAND gate is connected to address
bits A19-A17.

Example:
A A A A
1 1 1 1
19

18

17

1 1 1 1
=F0000H
1 1 1 1
=FFFFFH

16

A15 A A13 A
x x x x
0 0 0 0

A11A10 A A8 A7 A6 A A
A3 A A A
x x x x
x x x x
x x x x
or
0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1

To
1 1 1 1

14

12

1 1 1 1

1 1 1 1

 PROM Address Decoder:

Another common decoder is bipolar PROM
ADV: Large no. of input connections- which
reduces the no. of other Circuits
74LS138 has 6 inputs for address
connections, PROM decoder may have more
inputs for address decoding
82S147 (512x8) PROM
9 address inputs and 8 data outputs
replace 74LS138 without extra 3-input
NAND gate

 PROM is a memory device that must be

programmed with the correct binary bit
pattern to select the eight EPROM memory
devices.
The PROM has nine address inputs that
select one of the 512 internal 8 bit memory
locations.
The remaining input CE bar must be
grounded.
The main advantage of PROM decoder is
that the address map can be easily changed
in the field.

 PLD programmable Decoders:

Recently PAL has replaced PROM address
decoders in the memory interface.
There are three types of PLDs that function in
the same manner, but have different.
PLA, PAL and GAL
Memory interface:
The 8086 differs from 8088 in three ways: 1.
data bus,
2. M/IO bar in 8086 is IO/M bar in 8088, and
3.BHE bar in 8086

 16 Bit Bus Control: Data bus of 8086 is twice as wide as the

bus for 8088.
So, the processor must able to write data to any 16 bit
location or any 8 bit location.
So, 16 bit data must be divided into two separate sections
that are 8 bits wide so the microprocessor can write to either
half or both halves.

BHE
FFFFF
FFFFD
--------High bank
-------00005
00003
00001

BLE
FFFFE
FFFFC
FFFFA
-------Low bank
-------00004
00002
00000

 8086 uses the BHE bar signal and A0

address bit or BLE bar to select one or both
banks of memory for the data transfer.
BHE

BLE(A0)

Function

Both banks enabled for a 16 bit transfer

High bank enabled for an 8 bit transfer

Low bank enabled for an 8 bit transfer

No bank enabled

 Bank selection is accomplished in two ways:

1.A separate write signal is developed to
select a write to each bank of the memory or
2. separate decoders are used for each bank.
Separate bank decoder is the least effective
way to decode memory address for 8086.
Separate Bank write strobe method is the
most effective way for address decoding.
This technique requires only one decoder to
select a 16 bit wide memory.

 This often saves money and reduces the

number of components in a system.
Here