Clustering and Circuit Partitioning

KL Partitioning (1/6)

Clustering

Given a gate-level circuit, the goal of circuit clustering is to

group gates into clusters and obtain the network of the
clusters.

KL Partitioning (2/6)

Why is circuit partitioning necessary?

Practical Problems in VLSI Physical Design

KL Partitioning (3/6)

Example: Partitioning of a Circuit

Input size: 48

Cut 1=4
Cut 2=4
Size 1=15 Size 2=16

Size 3=17

[Sherwani]

Hierarchical Partitioning
Levels of partitioning:
System-level partitioning:
Each sub-system can be designed as a single PCB
Board-level partitioning:
Circuit assigned to a PCB is partitioned into subcircuits
each fabricated as a VLSI chip
Chip-level partitioning:
Circuit assigned to the chip is divided into
manageable sub-circuits

[Sherwani]

System Hierarchy

Levels of Partitioning
System
System Level Partitioning
PCBs
Board Level Partitioning
Chips
Chip Level Partitioning
Subcircuits
/ Blocks

Delay at Different Levels of

Partitions
A

x
B
10x

D
C

PCB1

PCB2
20x

Off chip wires are undesirable due to several reason

i.Performance degradation
ii.Takes area on a PCB
iii.Reduces the reliability of the system
iv.Since off chip wires must originate and terminate in to I/O
pins, more off chip wire essentially means more I/O pins.

[Sherwani]

Circuit partitioning

KL Partitioning (9/6)

Problem Definition

Definition: Given a graph G(V, E) edge weighted undirected graph, where each vertex
v V has a size s(v), and each edge e E has a weight w(e), the problem is to divide
the set V into k subsets Vl, V2, . . . , Vk, such that an objective function is optimized,
subject to certain constraints.

KL Partitioning (10/6)

The size s(v) of a node v represents the area of the

corresponding circuit element. Suppose that the circuit is
partitioned into k sub-circuits. The partition divides the graph
G(V, E) into k subgraphs Gi (Vi,Ei ) i, = 1 , 2 ,. . . ,k .

if we partition the circuit into two sub-circuits G1 and G2,

with gates 2,3,4 in one and gates 1,5,6 into another, the
subgraph G1 consists of nodes 2,3,4 and edges (2,4) and (2,3).
The subgraph G2 consists of nodes 1,5,6 and edge (5,6).
What about the edges (5,4), (1,2), and (4,6)? We say these
edges are cut by the partition.
The name cutset is used to describe the set of these edges. The
cutset of a partition is indicated by and is equal to the set of
edges cut by the partition, here {(1,2)(4,5)(4,6)}.

KL Partitioning (11/6)

Cost functions and Constraints

A cut set is the collection of all cut edges.

KL Partitioning (12/6)

Cost Functions and Constraints

Bounded size partitions

Minimize external wiring
Delay due to partitioning
Number of terminals
Number of partitions

Bounded size partitions

Circuit partition arises due to size restriction on circuit packages.
Again referring to the circuit of previous Fig., suppose that the six
gates occupy too much area to be included on a single chip. In
order to package this circuit, it must be split into two or more subcircuits. In the general k-way partitioning problem, the size
constraint is expressed by placing an upper bound on the size of
each sub-circuit.
Each sub-circuit has an upper bound on size. The size of the ith
sub-circuit is,
s(v) Ai
vVi

It is desirable to divide the circuit into roughly equal sizes.

1
1

s
(
v
)

k
k vV

Vi s (v)
vVi

where |Vi| and |V| are the sizes of the set Vi and V respectively.

Minimum external wiring

It is highly desirable to minimize the external wiring. The weight
w(e) on an edge e of the circuit graph represents the cost of wiring
the corresponding connection an external wire. Therefore, the cost
function that must be minimized during partitioning is,

KL Partitioning (15/6)

Algorithms for Partitioning

Circuit partitioning is NP-hard problem, means as the problem

size grows linearly, the effort needed to find an optimal
solution grows faster than any polynomial function.
To date, there is no known polynomial-time, globally optimal
algorithm for balance constrained partitioning. Several
efficient heuristics developed in the 1970s, 80s find highquality circuit partitioning solutions and in practice are
implemented to run in low-order polynomial time Kernighan and Lin (1970)
Fiduccia and Mattheyses Algorithm (1982)
EIG Algorithm (Hagen and Kahng, 1992)
FBB Algorithm (Yang and Wong, 1996)
KL Partitioning (16/6)

KL Algorithm

An iterative and efficient heuristic algorithm that solve the NP

hard balanced biparttioning problem, where the given gate-level
circuit is divided into two equal-sized partitions.

Limitations

It minimizes the no. of edge cut not the no of nets cut

A two-way (bisection) partitioning algorithm
The partitions must be balanced (of equal size)
Expensive in computation
Study shows that it is not possible to assign the weight to edges of
undirected graph (Ihler et. al. 1993).
KL Partitioning (17/6)

KL Algorithm Pseudo code (Home Work)

KL Partitioning (18/6)

Kernighan-Lin Algorithm

Given partition {abde,cfgh} as an initial partition

perform a single pass of perform single KL pass on the
following circuit. Break ties in lexicographical order.

KL needs undirected graph (assume clique-based weighting)

Edge weighted undirected graph

KL Partitioning (19/6)

First Swap

gD
2C
x
y
xy
Cut size or cost function= 5

KL Partitioning (20/6)

Second Swap

Cut size = 3

KL Partitioning (21/6)

Third Swap

Cut Size = 3

KL Partitioning (22/6)

Fourth Swap

Last swap does not require gain computation

Cut size = 4

Cut size = 5

KL Partitioning (23/6)

Summary

Give the cutsize after each swap? What are the initial, the
final and the best cutsizes covered during the pass.
Two best solutions found (solutions are always area-balanced)
If gain > 0; cut cost
If gain < 0; cut cost
Known as look ahead Algo.

KL Partitioning (24/6)

A Graph in form of Connectivity Matrix

1
5
6

Cii = Cjj =0

2
3
Assume network with
same sizes and each
edge has a weight
assign to 1.
0 10000
101100

C11 C12 C13 C14 C15 C16

C21 C22 C23 C24 C25 C26
C31 C32 C33 C34 C35
C41 C42 C43 C44 C45
C51 C52 C53 C54 C55
C61 C62 C63 C64 C65

C36
C46
C56
C66

01000 0
010011
00010 1
00011 0

If all connections are equal in importance the elements of the cost matrix are
1 or 0, costs may be higher than 1 also.
KL Partitioning (25/6)

An edge weighted graph is not the exact model of a network for partitioning

n4
n1

n2

n3
n5

KL Partitioning (26/6)

Modeled into a Hypergarph

KL Partitioning (27/6)

Hypergraph

(Ref. Wikipedia)

A hypergraph is a generalization of a
graph in which an edge can connect
any number of vertices. A hypergraph H
is a pair H(X, E), where X is a set of
elements called nodes or vertices and E
is a set of non empty subsets of X
called hyper edges or edges.

KL Partitioning (28/6)

References
1.

2.

3.

4.
5.

6.

An efficient Heuristic procedure for partioning graphs

by B. W Kernighan & S. Lin.
VLSI physical design from graph partitioning to timing
closure by Kahng et al.
Practical problems in VLSI physical design by Sung
Kyu Lim.
VLSI physical design Automation by Sait and Youssff.
ASIC book by M. J. S. Smith, Addision Wesley
publisher.
Hypergraph from Wikipedia.

KL Partitioning (29/6)