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CMOS VLSI
Design
Lecture 3:
CMOS Transistor Theory
David Harris
Outline
Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
Pass Transistors
RC Delay Models
Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed
Also explore what a degraded level really means
MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
Vg < 0
+
-
polysilicon gate
silicon dioxide insulator
p-type body
(a)
0 < Vg < Vt
depletion region
+
-
(b)
V g > Vt
inversion region
depletion region
+
-
(c)
Terminal Voltages
Mode of operation depends on Vg, Vd, Vs
Vgs = Vg Vs
Vgd = Vg Vd
Vds = Vd Vs = Vgs - Vgd
Vg
+
Vgd
-
+
Vgs
Vs
Vds
Vd
nMOS Cutoff
No channel
Ids = 0
Vgs = 0
+
-
+
-
Vgd
n+
n+
p-type body
b
nMOS Linear
Channel forms
Current flows from d to s
V
e- from s to d
Ids increases with Vds
Similar to linear resistor
gs
> Vt
+
-
+
-
Vgd = Vgs
n+
Vds = 0
n+
p-type body
b
Vgs > Vt
+
-
+
d
n+
n+
p-type body
b
nMOS Saturation
+
-
+
-
Vgd < Vt
d Ids
n+
n+
p-type body
b
I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel?
How fast is the charge moving?
Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel =
gate
Vg
polysilicon
gate
W
tox
n+
n+
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
3: CMOS TransistorSlide
Theory
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Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel = CV
C=
gate
Vg
polysilicon
gate
W
tox
n+
n+
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
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Theory
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Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel = CV
Cox = ox / tox
C = Cg = oxWL/tox = CoxWL
V=
gate
Vg
polysilicon
gate
W
tox
n+
n+
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
3: CMOS TransistorSlide
Theory
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Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel = CV
Cox = ox / tox
C = Cg = oxWL/tox = CoxWL
V = Vgc Vt = (Vgs Vds/2) Vt
gate
Vg
polysilicon
gate
W
tox
n+
n+
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
3: CMOS TransistorSlide
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Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
v=
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Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
v = E
called mobility
E=
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Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
v = E
called mobility
E = Vds/L
Time for carrier to cross channel:
t=
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Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
v = E
called mobility
E = Vds/L
Time for carrier to cross channel:
t=L/v
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I ds
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Qchannel
I ds
t
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Qchannel
I ds
t
W
Cox
L
V V Vds V
gs t
ds
2
V
Vgs Vt ds Vds
2
CMOS VLSI Design
W
= Cox
L
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I ds
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I ds Vgs Vt
Vdsat
Vdsat
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I ds Vgs Vt
Vgs Vt
2
Vdsat
Vdsat
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Vgs Vt
Vds
I ds Vgs Vt
Vds Vds Vdsat
Vgs Vt
Vds Vdsat
2
CMOS VLSI Design
cutoff
linear
saturation
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Example
We will be using a 0.6 m process for your project
From AMI Semiconductor
tox = 100
2.5
V =5
= 350 cm2/V*s
2
Vt = 0.7 V
1.5
V =4
Plot Ids vs. Vds
1
Ids (mA)
gs
Vgs = 0, 1, 2, 3, 4, 5
Use W/L = 4/2
3.9 8.85 1014
W
Cox 350
L
100 108
gs
Vgs = 3
0.5
0
W
W
120
A /V 2
L
L
Vgs = 2
Vgs = 1
Vds
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pMOS I-V
All dopings and voltages are inverted for pMOS
Mobility p is determined by holes
Typically 2-3x lower than that of electrons n
120 cm2/V*s in AMI 0.6 m process
Thus pMOS must be wider to provide same current
In this class, assume n / p = 2
*** plot I-V here
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Capacitance
Any two conductors separated by an insulator have
capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion
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Gate Capacitance
Approximate channel as connected to source
Cgs = oxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/m
polysilicon
gate
W
tox
n+
n+
p-type body
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Diffusion Capacitance
Csb, Cdb
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to Cg
for contacted diff
Cg for uncontacted
Varies with process
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Pass Transistors
We have assumed source is grounded
What if source > 0?
VDD
e.g. pass transistor passing VDD
VDD
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Pass Transistors
We have assumed source is grounded
What if source > 0?
VDD
e.g. pass transistor passing VDD
VDD
Vg = VDD
If Vs > VDD-Vt, Vgs < Vt
Hence transistor would turn itself off
nMOS pass transistors pull no higher than VDD-Vtn
Called a degraded 1
Approach degraded value slowly (low Ids)
pMOS pass transistors pull no lower than Vtp
CMOS VLSI Design
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VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
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VDD
VDD
VDD
Vs = VDD-Vtn
Vs = |Vtp|
VDD
VDD
VDD
VDD-Vtn VDD-Vtn
VDD
VDD-Vtn
VDD-Vtn
VDD
VSS
VDD-2Vtn
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Effective Resistance
Shockley models have limited value
Not accurate enough for modern transistors
Too complicated for much hand analysis
Simplification: treat transistor as resistor
Replace Ids(Vds, Vgs) with effective resistance R
Ids = Vds/R
R averaged across switching of digital gate
Too inaccurate to predict current at any given time
But good enough to predict RC delay
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RC Delay Model
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
d
d
k
s
s
kC
R/k
g
kC
kC
s
d
k
s
kC
2R/k
kC
kC
d
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RC Values
Capacitance
C = Cg = Cs = Cd = 2 fF/m of gate width
Values similar across many processes
Resistance
R 6 K*m in 0.6um process
Improves with shorter channel lengths
Unit transistors
May refer to minimum contacted device (4/2 )
Or maybe 1 m wide device
Doesnt matter as long as you are consistent
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2 Y
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2 Y
2C
2C
Y
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2 Y
2C
2C
2C
2C
Y
R
R
C
C
C
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2 Y
2C
2C
2C
2C
Y
R
R
C
C
C
d = 6RC
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