Combinational Circuits

CS2052 Computer Architecture

Computer Science & Engineering
University of Moratuwa

Dilum Bandara
Dilum.Bandara@uom.lk

Blocks of a Microprocessor
Program Execution Section

Register Processing Section

Literal
Address
Operation

RAM &
Data
Registers

Accumulator
Instruction
Register

Program
Memory

Address
STACK

Program Counter

Modify
Clock
Reset
Interrupts

IO

Internal data bus

ALU
Instruction
Decoder
Set up

FLAG &
Special
Function
Registers

Set up

Timing, Control and Register selection

2

Source: Makis Malliris & Sabir Ghauri, UWE

IO

Combinational Circuits
n inputs

Combinational
Circuits

m outputs

Binary values of outputs are a function of binary

combination of inputs
Outputs at any given time are entirely dependent
on inputs that are present at that time

Adding 2 Numbers

Write the truth table for addition of 2 bits A & B

A

Sum (S)

Carry (C)

Write Boolean representation for Sum & Carry

S = A/B + AB/ = A B
C = AB
4

Adding 2 Numbers (Cont.)

Draw logic circuit

Source: Wikipedia.org

This is called a half adder

Adding 2 Numbers & a Carry

Write the truth table for addition of 2 bits A & B

as well as a carry from previous low-order bit
A

Cin

Cout

1
6

Adding 2 Numbers & a Carry (Cont.)

Write Boolean representation for Sum & Carry

Hint use k-maps

S = (A B) Cin

Cout = AB + (A B)Cin

c
ab

S=

c
ab

00

00

01

01

Cout =
11

11

10

10

07

Adding 2 Numbers & a Carry (Cont.)

Draw logic circuit

Source: www.setupsolution.com/how-to-design-a-half-adder-and-full-adder-in-verilog-at-gate-level-modeling/

This is called a full adder

8

Schematic Representation of Full

Adder
(A B)
AB

Source: http://en.wikibooks.org

n-bit Adder (Ripple Carry Adder)

10

Decoders

Suppose a simple microprocessor supports

following 2 instructions

ADD

LOAD

When these instructions execute theyll need to

activate different circuits

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Which circuit is determined by 2 most significant
bits

Decoders
b0
b1

Decoder

d0 Adder
d1
d2 Loader
d3

Converts binary data from n coded inputs to a

maximum of 2n unique outputs
Called n-to-2n decoder

12

Decoders

Truth table for a 2-to-4 decoder

b0

b1

d0

d1

d2

d3

13

Decoders

Draw logic circuit of a 2-to-4 decoder

b0
b1

d0
d1
d2
d3

Source: www.allaboutcircuits.com/vol_4/chpt_9/4.html

14

3-to-8 Decoder

Source: www.edwardbosworth.com/CPSC2105/Lectures/Slides_05/Chapter_03/DecodersAndMux.htm
15

Decoder Expansion

Build a 3-to-8 decoder using 2-to-4 decoders

Source: http://dc167.4shared.com/doc/
or00nekd/preview.html

Source: www.teachurselfece.com/2012/
02/decoders.html
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Decoders (Cont.)

ADD

LOAD

Also helps us select which registers to use

17

Address Bus

Use of Decoders Inside CPU

B
PC
C

+1

Data Bus

ALU

D
IR

CTRL Bus

Control Unit

ALU
FLAG
A
18

Encoders

Reverse process of a decoder

4-to-2 encoder
3-to-8 encoder

Source: www.electronics-tutorials.ws/combination/comb_4.html

19

Encoders

Draw logic circuit of a 4-to-2 encoder

D3

Q0

D2
D1

Q1

D0

20

Priority Encoder

Source: www.electronics-tutorials.ws/combination/comb_4.html

21

Address Bus

Internal Structure
B
PC
C

+1

Data Bus

ALU

D
IR

CTRL Bus

Control Unit

ALU
FLAG
A
22

Internal Structure (Cont.)

Source: www.transtutors.com/homework-help/computerscience/computer-architecture/cpu/general-register-organization/

23

Multiplexer
d0
d1
d2
d3

Multiplexer

s0

s1

Receives binary data from 2n lines & connect

them to a single output line based on a selection
By applying a control signals we can steer any
input to the output

24

Multiplexer (Cont.)

Truth table
s0

s1

d0

d1

d2

d3

25

Multiplexer (Cont.)

Logic circuit
d0
d1
d2

d3

Source: www.ee.surrey.ac.uk/Projects/CAL/digital-logic/multiplexer/index.html
26

8-to-1 Multiplexer

27

Source: http://users.cis.fiu.edu/~prabakar/cda4101/Common/notes/lecture08.html

8-to-1 Multiplexer using 4-to-1 & 2-to-1

Multiplexers

Source: www.exploreroots.com/dc28.html
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Demultiplexer
d

Demultiplexer

s0

q0
q1
q2
q3

s1

Reverse process of a multiplexer

By applying a control signals we can steer the
input signal to one of the output lines

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Demultiplexer (Cont.)

Truth table

Logic circuit

s0

s1

q0

q1

q2

q3

d
d

q0

q1

q2
q3

Source: http://do-area.blogspot.com/p/multiplexer-demultiplexer.html

s0 30s1

Demultiplexer Using Decoder

Source: http://en.wikipedia.org

31

Multiplexer/Demultiplexer Application in Telecommunication

Source: http://digilogwiki.com/index.php?title=Multiplexers/Demultiplexers
32

Summary

Source: www.transtutors.com/homework-help/computerscience/computer-architecture/cpu/general-register-organization/

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