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Terminology
task
subtask
stage
staging register
Tpl =
, where ti is the processing time,
di is the delay by the staging register, and k is the
number of stages
i 1
(ti di )
i 1
i 1
Pipeline Types
arithmetic pipelines
processor pipelines: a cascade of
processors each executing a specific
module in the application program.
Instruction pipeline
reservation table
Row : stages
Column : pipeline cycles
Control Hazard
Arithmetic pipelines
Arithmetic pipelines(cont.)
Add exponents
Multiply mantissas
Normalize Mp and adjust Ep
Round Mp
Renormalize Mp and adjust Ep
Arithmetic pipelines(cont.)
Multifunction pipeline
To perform more than one operation
A control input is needed for proper
operation of the multifunction pipeline.
Figure 3.10 : floating point add/multiplier
Classification scheme by
Ramamoorthy and Li
Functionality
unifunctional
multifunctional
Configuration
static
dynamic
Mode of operation:
scalar
vector
Structural hazard
Due to the non-availability of
appropriate hardware
One obvious way of avoiding structural
hazard is to insert additional hardware
into the pipeline.
Example 3.3
Collision vectors
Collision vectors(cont.)
CV = (vn-1,vn-2,,v2,v1)
Vi =1 if i is in the forbidden set
Examples
Example 3.4
(a) Overlapped RT
(b) Collision Vector(CV)
Control
3.2.3 Performance
Figure 3.15(a)
The CV of Figure 3.11 : (00111)
Figure 3.15(a) shows the state transitions.
3.2.3 Performance
Average latency
simple cycle
greedy cycle
MAL(Minimum average Latency)
write-read forwarding
read-read forwarding
write-write forwarding
Conditional Branches
branch prediction
delayed branch
branch-prediction buffer
branch history
multiple instruction buffers
Interrupts
precise interrupt scheme
Instruction deferral
scoreboard
Tomosulos algorithm
Performance evaluation
3.6 Summaries
End of Chapter 3