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Analog and Mixed Mode VLSI Design 06EC63

Unit I
Data Converter
Fundamentals

Session: Jan – June 2010


Terminology
analog: continuously valued signal, such as temperature
or speed, with infinite possible values in between.
Analog data (All values on the time and amplitude are allowed).

digital: discretely valued signal, such as integers, encoded


in binary. Digital data (Only a few amplitude levels are allowed).
Introduction
-Signals in real world; light, sound .

-When you scan a picture with a scanner what the


scanner is doing?? (ADC)
It is taking the analog information provided by the
picture (light) and converting into digital .

-When you record your voice on your computer.


Introduction cont'd
- Since analog signals can assume any value, noise is
interpreted as being part of the original signal. Digital
system, on the other hand, can only understand two
numbers, zero and one. Anything different from this is
discarded.

- Here we need a translator from analog to digital. The


devices which play this job are called analog to digital
converter.
Analog-to-digital converter
-An analog-to-digital converter (abbreviated ADC,
A/D or A to D or A2D) is an electronic circuit that
converts continuous signals to discrete digital
numbers.
-The digital output may be using different coding
schemes, such as binary and two's complement
binary. However, some non-electronic or only
partially electronic devices, such as shaft encoder,
can also be considered as ADCs.
Analog-to-digital converters
Vmax = 7.5V 1111 4 4
7.0V 1110
6.5V 1101 3 3

analog output (V)


analog input (V)
6.0V 1100
5.5V 1011
2 2
5.0V 1010
4.5V 1001
4.0V 1 1
1000
3.5V 0111
3.0V 0110 time time
t1 t2 t3 t4 t1 t2 t3 t4
2.5V 0101
2.0V 0100 0100 0110 0110 0101 0100 1000 0110 0101
1.5V 0011 Digital output Digital input
1.0V 0010
0.5V 0001
0V 0000

proportionality analog to digital digital to analog

Embedded Systems Design: A Unified


Hardware/Software Introduction, (c) 2000 Vahid/Givargis
Example:
 You live in Moscow, Idaho, where the weather in the
winter stays between 0 °F and 50 °F (Fig. 28.2a).
 Suppose you had a thermometer that contained only
two readings on it, hot and cold, and that you
wanted to record the weather patterns and plot the
results The two quantization levels can be correlated
with the actual temperature as follows:
 If 0°F ≤ T ≤ 25°F Temperature is recorded as cold
 If 25°F≤ T ≤ 50°F Temperature is recorded as hot
 You take a measurement every day at noon and plot
the results after one week
Example contd…
Example contd…
Note:
 The accuracy of the digitized signal is
dependent on two things:
 the number of samples taken and
 The resolution, or number of quantization
levels of the converter.
 In our example, we need to increase both
the number of samples and the resolution
of thermometer.
Example contd…
 We obtain a thermometer with 25
temperature readings and that we now
take a reading eight times per day.
 Each of the 25 quantization levels now

represents a 2 °F band of temperature


How many samples should one take in order to
accurately represent the analog signal?
 Suppose a sudden rainstorm swept through
Moscow and caused a sharp decrease in
temperature before returning to normal.
 If that storm had occurred between our
sampling times, our experiment would not
have shown the effects of the storm. If
sampling time was too slow to catch the
change in the weather.
 If we had increased the number of samples,
we would have recognized that something
happened which caused the temperature to
drop dramatically during that period.
Nyquist Criteria
 the sampling rate be at least two times the
highest frequency contained in the analog
signal.
 In our example, we need to know how quickly
the weather can change and then take
samples twice as fast as that value.
 The Nyquist Criterion can be described as
Fsampling = 2 F MAX
How much resolution should we use to
represent the analog signal accurately?
 There is no criterion for this specification.
 Each application will have its own requirements.
 In our weather example,
 if we were only interested in
following general trends,
then the 25 quantization
levels would more than
suffice.
 However, if we were
interested in keeping an
accurate record of the
temperature to within ±0.5
°F, we would need to double
the resolution to 50
quantization levels so that
each quantization level
would correspond to each
degree ±0.5 °F .
Note:
 Sampling depends on the frequency of the
signal.
 Quantization depends on amplitude of the
signal.
 The rate of sampling and the no. of
quantization levels do not have any
relation with each other.
Sample and Hold Characteristics
 Behavior is analogous to that of a camera.
 Function: To sample the analog signal and
hold it until the ADC processes it.
 Limits both speed and accuracy.
 It operates in both
 Dynamic (sample) and
 Static (hold) circumstances
Track and Hold Circuit

 Analog Signal continues to vary in between the sampling periods.

 In S/H circuit : Impulse functions are utilized for sampling.


 In T/H circuit : Complete tracking time itself is sampling time.
Major Errors associated with S/H Circuit

 Op-amp:
 Matching of impedance such that the capacitor doesn’t discharge
into the load.
 Response dependent on slew rate, sampling will not be
instantaneous at the output.
Major Errors associated with S/H Circuit: Sampling Mode
 Acquisition Time: Time taken by the S/H ckt.
To track the analog signal, after the issue of the
sampling command.
 Cause: Improper compensation & smaller phase
margin of the op-amp’s closed loop gain.
 Worst case: Time required for the o/p to have
transition from zero to Vin(max).
 Comprises of Overshoot and Settling Time.
 Overshoot: Normalized difference b/w the time
response peak & the steady o/p.
 Settling Time: Time required for the response to reach
& stay within a specified tolerance band (usually 2%
or 5%) of its final value.
Major Errors associated with S/H Circuit: Hold Mode
 When control signal is removed, the switch turns off &
capacitor holds the sampled value.
 Pedestal Error.
 Droop.
 Aperture Error.
Major Errors associated with S/H Circuit: Hold Mode
 Pedestal Error:
 Def: Slight reduction in the o/p voltage, after
the removal of the control signal.
 Cause: Charge injection onto CH as MOSFET
is turned off.
 Droop:
 Def:Gradual reduction in the o/p voltage.
 Cause: Leakage of current from CH .

 reduced by CH , but it Acquisition time.


 Max. allowable droop is ½ LSB.
Major Errors associated with S/H Circuit: Hold Mode
Aperture Error / Aperture jitter / Aperture Uncertainty
 Occurs between sample &
hold modes.
 Cause:
 MOSFET doesn’t turn off until
gate-voltage reached below
Vt.“ Aperture time”.
 Switching noise in control
signal.
 Worst case: At Zero
crossing( dV/dt is max).
 So, resolution of conversion
is affected.
Ex.1) A periodic sinusoidal signal has maximum
amplitude of 2V & frequency of 100KHz. If the
aperture uncertainty is equal to 0.5ns, find the
max. sampling error.
 Slew Rate = dV/dt
 dV(max)/dt =
 Max. Sampling Error =dV(max)
 Ans: 0.628mV
Ex.2) A S/H ckt. is supposed to have a max.
sampling error of 1mV, with the aperture jitter of
1ns. If the freq. of the signal is 50KHz, find its
max. possible amplitude.
 Given: dV(max) = 1mV, dt = 1ns.
 Vin = A sin (2πf)t
 Substitute values in dV/dt = A (2 π f) x cos(2πf)t

Ans: 3.18V
DAC Specifications contd.
Resolution
 Def: The smallest change in voltage which can be
produced at the output (or input) of the converter.
 No. of Quantization levels corresponds to resolution.
 For DAC:
 8 bit DAC has 28-1 = 255 equal intervals.
 Smallest change in output voltage is (1/255) of full
scale output range. = 0.392 = 1LSB.
 It is stated in no. of ways:
 8 bit resolution.
 A resolution of 0.392 of full scale
 A resolution of 1 part of 255.
DAC Specifications contd.
Resolution
 For ADC: smallest change in analog input for a one bit
change at the output.
 8 bit ADC: is divided into 255 intervals.
 Resolution for a 10V input range is 39.22mV (= 10/255 V)
DAC Specifications
 O/P voltage of DAC
VOUT = F. VREF

 F = D / 2N

where, D = Input word.


N = No. of bits
in the word.
2N= No. of input
combinations
Ex.3) If a 3 bit DAC is considered with Vref = 5V,
and if the input word is 110, then Vout is

 Vout = {(110)2/ 23 } x5
=(6/8)x5
=3.75V

 Thus , the max analog o/p for this DAC can be,
Vout(max) = (111) 2/ 23 x 5 = 4.375V
DAC Specifications contd.
DAC Specifications contd.
Note
 Full Scale Voltage:
VFS = {(2N-1)/ 2N } x VREF
 Resolution: 1 LSB = VREF / 2N
 More no. of i/p bits results in smaller changes in o/p voltage & thus
yielding better resolution.

Hence, in case of data-converters,


the resolution is expressed in terms of the no. of bits.
Also, Accuracy of DAC = 1 / 2N
DAC Specifications contd.
 Ex.4) Given VREF of a DAC is 5V & the o/p
voltage increment desired is 1mV, find the
resolution of the DAC.
 Ans: using formula :1 LSB = VREF / 2N

 N= 12.29 bits = 13
DAC Specifications contd.
 Ex. 5) A digitally programmable signal generator
uses a 14 bit DAC with a 10V reference. Find a)
Smallest incremental change at the o/p. b) DAC’s
Full scale value. c) The accuracy.
 Ans: a)1LSB = 610µV.

 b) VFS = 9.9993V
 c) Accuracy = 0.0062%
DAC Specifications contd.
 DIFFERENTIAL NONLINEARITY ERROR (DNL)
 Cause : Non-linear components within DAC cause increments to
differ from their ideal values.
 Def: The difference between the ideal and non-ideal values of the
increments.
DNLn = (Actual increment of transition n) –(Ideal increment height)
 Where, n = No. corresponding to digital i/p transition.
DAC Specifications contd.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
DAC Specifications contd.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
 Points to remember:
 DNL ≤ ± ½LSB. “Monotonic” i.e. the analog o/p does increment as
digital input code is incremented.
 IfDNL = ± 1 LSB, then DAC is called as “non– monotonic”.
 A 5-bit DAC with 0.75 LSBs DNL actually has resolution of 4-
bit DAC.
 So, DAC should exhibit montonicity to work without error.
 The overall error of DAC is defined by its worst case DNL.
DAC Specifications contd.
INTEGRAL NONLINEARITY ERROR (INL)
 Def: The difference between the data converter o/p values &
the corresponding points on the reference line drawn through
the first & last o/p values.
INLn = (O/p value for i/p code n) – (o/p value on the
reference line)
DAC Specifications contd.
INTEGRAL NONLINEARITY ERROR (INL)
 DNL is defined in accordance with the increment height.
i.e. the previous position.
 INL defined in accordance with the slop of the curve. i.e.
the transition line.
INL = (Actual o/p voltage) – (Ideal o/p voltage)
Note:
o Using the value of VREF & resolution it is possible to

express DNL & INL in terms of volts as well.


o Normally assumed that a DAC will have < ± ½LSB of
DNL & INL.
DAC Specifications contd.
INTEGRAL NONLINEARITY ERROR (INL)
DAC Specifications contd.
INTEGRAL NONLINEARITY ERROR (INL)
Q. Determine the maximum DNL (in LSBs) for a 3-bit DAC, which
has the following characteristics. Does the DAC have 3-bit
accuracy? If not, what is the resolution of the DAC having this
characteristic?
Q. Repeat the above problem for calculating the INL (in
LSB’s).
 The maximum magnitude INL is at
010 and at 110 where the actual
analog output is 0.3125 above the
line and 0.3125 below the line,
respectively.
 These INLs convert to ± ½LSB
after dividing by VREF /8 (1LSB).
 The worst INL is ½ LSB and 3-bit
accuracy is 1LSB,
 so yes, it has 3-bit accuracy.
Q. A DAC has a reference voltage of 1,000V, and its
maximum INL measures 2.5mV. What is the maximum
resolution of the converter assuming that all the other
characteristics of the converter are ideal?
 Assume that a converter with N-bit resolution will have less than ±0.5LSB of INL and DNL.
 So, finding

 Also,

Answer will be N= 18 as when we substitute 17 in INL(max) it is greater than 2.5mV


ADC Specifications
 Process complex than DAC.
 Infinite no. of input values.
 Quantization of 2N levels.
 Transfer curve reverse of
that of DAC.
ADC Specifications
ADC Specifications
Quantization Error QE
 Def: The difference betn the actual analog input & the value of the staircase o/p.
QE= VIN – Vstaircase

 Where, Vstaircase = D. VLSB


 VLSB = VREF / 2N

 D = o/p ‘s coe’s value in decimal


 QE (max)= 1 LSB for above curve.
ADC Specifications

Quantization Error QE reduced by 50%


ADC Specifications

Quantization Error QE reduced by 50%


 QE (max)= 0.5 LSB
 Transitions occur in betn two quantization levels.
 However, last transition occurs betn 6/8 and 7/8.
 Also, step–width is 1.5 times larger than
previous ones. Hence, QE (max)= 1LSB. But it
occurs at max. amplitude of the i/p signal. The
converter considered out of range, for F ≥ 15/16.
 Hence, QE (max) remains = 0.5 LSB
ADC Specifications

DNL
 Def: The difference betn the actual code width
of a non-ideal converter & the ideal case.

DNL = (Actual Step width – Ideal Step width)


ADC Specifications
Q.Plot the transfer curve for the 3-bit ADC
with VREF = 5V & with the following analog
inputs: 0.3125V,0.9375V,
1.875V,2.1875V, 2.8125V, 3.125V,
4.0625V, 5.0V. Determine its DNL also.
ADC Specifications
Ans :
ADC Specifications
IMP points derived
 Quantization error directly related to the
DNL.
 As DNL increases in either direction, the
quantization error worsens.
 Each “tooth“ in the quantization error
waveform should ideally be the same size.
ADC Specifications
Missing codes
 In transfer curve, ideally,
height remains constant.
 But, if any step width
becomes 2 LSB or more
then the height gets
increased.
 Cause: ADC tries to follow-
up with the slope of the ideal
line.
 Occurrence : when DNL
exceeds ± 1 LSB
ADC Specifications

INL
 Def: The difference between the data-
converter code transition points & the ideal
straight line.

INL = (Actual transition – Ideal transition)


ADC Specifications
Determine the INL for the ADC whose. VREF = 5V & with the
following analog inputs: 0.3125V,0.9375V, 1.875V,2.1875V,
2.8125V, 3.125V, 4.0625V, 5.0V. Determine its INL also. Draw
the quantization error, Q, in units of LSBs.
ADC Specifications
Q. Plot the transfer curve for the 3-bit ADC with VREF
= 5V & with the following analog inputs : 0.3125V,
1.25V, 1.875V, 2.1875V, 3.4375V, 4.375V, 4.6875V,
5.0V. Determine its INL as well.
ADC Specifications
Problem contd..
ADC Specifications

OFFSET ERROR & GAIN ERROR


ADC Specifications
Aliasing

• Analog signal sampled at a rate slower than the Nyquist criteria requires.

• A totally different signal of lower frequency (dashed line) is being sampled


actually.

• the lower frequency signal is an “alias” of the original signal, its frequency
given by falias = factual - fsample
ADC Specifications
Aliasing
 Elimination Techniques:
 Sampling at higher frequencies.
 Filtering the analog signal before sampling &
removing any frequencies that are greater than half
the sampling frequency.
 Removes unknown higher order harmonics or noise.
 However, adds delay to overall conversion.

 Therefore, combination of both methods are used.


ADC Specifications
Aliasing
ADC Specifications
SIGNAL TO NOISE RATIO
 Def: represents the ratio of largest RMS input signal value
into the converter over the RMS value of noise. Unit : dB.
 SNR = 20 log(vin(max) / vnoise )

 Input signal, vin(max) = 2N. VLSB = VREF


 Therefore, vin(max)RMS = 2N. VLSB / 2√2 (=Vp-p )
 RMS of Noise is Qe(RMS) = VLSB / √12 (as sawtooth
waveform)
 SNR = (6.02N + 1.76)dB
ADC Specifications
SIGNAL TO NOISE RATIO contd…
 SNR = (6.02N + 1.76)dB
 Relates SNR to resolution
 To find:
 Resolution
 calculating SNRD(Signal to noise ratio with
Distortion ratio)
 As o/p is digital so can’t use Spectrum
Analyzer to calculate ratio, but use
DFT(Discrete Fourier Transform)
ADC Specifications

Q. An ADC has a stated SNR of 94dB.


Determine the resolution of the converter.
 Given 94 = 6.02N + 1.76
 Therefore, N = (94 – 1.76) / 6.02
 =15.32 bits
ADC Specifications
APERTURE ERROR
 = SAMPLING ERROR IN S/H CKT.
 Related to ADC characteristics.
 Max. errors associated are related to
0.5LSB.
 Aperture error can be no longer than
0.5LSB.
ADC Specifications
Q. Find the maximum resolution of an ADC
which can use the S/H having aperture
uncertainty of 0.628mV, while maintaining a
sampling error less than 0.5LSB.
 Ans. 0.628mV ≤ 0.5LSB

= VREF / 2N+1

= 5/ 2N+1

Now, 2N+1 ≤ 7.961.8


Solving for N limited to an integer, N =11
MIXED SIGNAL LAYOUT ISSUES
 Analog ICs more sensitive to noise than digital.
 Therefore, Layout to be done carefully.
 So having both digital & analog at one single
chip requires lot of attention & care.
 Eg: Majority of ADCs uses switches controlled
by digital signal, so separate routing channels
needs to be provided.
 A successful mixed-mode design will always
minimize the effect of digital switching on the
analog circuits.
MIXED SIGNAL LAYOUT ISSUES
MIXED SIGNAL LAYOUT ISSUES
Integrated IC at NASA

The integrated circuit from an Intel


8742, an 8-bit microcontroller that
includes a CPU running at 12 MHz,
128 bytes of RAM, 2048 bytes of
EPROM, and I/O in the same chip.
MIXED SIGNAL LAYOUT ISSUES

Integrated circuit of
Atmel Diopsis 740
System on Chip
showing memory blocks,
logic and input/output
pads around the
periphery
MIXED SIGNAL LAYOUT ISSUES

• Techniques used to increase the success of mixed-signal designs vary


in complexity & priority.
• Lowest issues are foundational & considered before each succeeding
step.
MIXED SIGNAL LAYOUT ISSUES
FLOORPLANNING
• Analog circuitry categorized by the
sensitivity of the analog signal to noise.
•Sensitive nodes: Low-level signals
or high impedance nodes typically
associated with input signals.
•High-swing analog ckts:
comparators & o/p buffer amplifiers.

• Digital Circuitry categorized by speed &


function.
•Digital o/p buffers designed to drive
capacitive loads at very high rates. So,
kept farthest from sensitive analog
signals.
•Then high & low speed digital ckt
should be kept.
MIXED SIGNAL LAYOUT ISSUES
POWER SUPPLY & GROUNDING
Danger: Injecting noise from digital system to the sensitive analog circuitry through
the power supply & ground connections.
How power supply & ground are supplied to both?
Ri1 & Ri2 = small & non-negligible resistance of the interconnect to the pad.
Ls1 & Ls2 = inductance of bonding wire which connects the pads to the pin on the lead
frame.
Voltage Spike :
1) Digital circuitry has high transient currents due to switching, small amount of
resistance associated with interconnect can result in significant spikes.
Low level analog signals sensitive to such interference, thus contaminating analog
system.
2)Inductance of the bonding wire. Voltage across the inductor α change in current
through it. Voltage spikes equating to hundreds of multi volts can result.
MIXED SIGNAL LAYOUT ISSUES
POWER SUPPLY & GROUNDING
MIXED SIGNAL LAYOUT ISSUES
POWER SUPPLY & GROUNDING
 Fig a) Serious degradation in analog circuitry
performance as power supply & ground bounces :
 For low-swing signals, when there are transient currents due to
high speed switching parasitic components become prominent :
 R = Resistance of the interconnect.
 L = Inductance of the bonding wire.
 Fig b) Parasitic resistance not common to digital &
analog circuitry, but inductance still remains.
 Fig c) two circuits completely decoupled, so low swing
analog cktary completely isolated from switching
transients.
 Disadv: pad count increases on die & pin count on lead frame.
NOTE: R↓ Power supply & gnd bus widest possible.
L ↓ Planning supply & gnd pins closest to die.
MIXED SIGNAL LAYOUT ISSUES
FULLY DIFFERENTIAL DESIGN

• i/ps & o/ps both designed to be differential.


• noise that gets coupled thru stray capacitances gets rejected(common mode nature)
•Common centroid & interdigitated techniques to match transistors in layout.
MIXED SIGNAL LAYOUT ISSUES
GUARDED RINGS

• Sensitive circuitry placed


inside a separate well.
• Well surrounded by guard
ring.
• Guard ring connected to
analog VDD , such that digital
switching noise effect
becomes minimum.
MIXED SIGNAL LAYOUT ISSUES
SHIELDING
Whenever low-level signal line crosses high speed digital line :
• Metal 1 placed in betn analog &
digital signals.
•Analog signal = Poly layer.
•Digital = Metal 2 Layer.
•Shielding Metal 1 connected to
analog ground.
MIXED SIGNAL LAYOUT ISSUES
SHIELDING CONTD.
• During routing, sensitive analog line in parallel with high speed digital line should
be avoided.
•A shielding to be provided whenever not possible.
MIXED SIGNAL LAYOUT ISSUES
OTHER INTERCONNECT
CONSIDERATIONS
• Strategies to improve performance of analog circuitry:
•minimal Length of analog current carrying line.
•Changing of layers →use contacts (minimizes
resistance in path & improves fabrication reliability).
•Avoid poly for routing current carrying signals.
•Use poly to route only high impedance gate nodes,
which carry no current.