CS601: Microprocessor &

Interfacing : UNIT 1
 Brief History of 8086
• The 8086 is a 16-bit microprocessor chip designed by
Intel and introduced on the market in 1978, which
gave rise to the x86 architecture.
• Intel introduced the 8086 as a cost effective way of
porting software from the 8080 lines, and succeeded
in winning much business on that premise.
• The 8088, a version of the 8086 that used an external
8-bit data bus.
• Following up their 8086 and 8088, Intel released the
80186, 80286 and, in 1985, the 32-bit 80386,
cementing their PC market dominance with the
processor family's backwards compatibility.

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 Features of 8086
Microprocessor
• 8086 has 16-bit ALU; this means 16-bit
numbers are directly processed by 8086.
• It has 16-bit data bus, so it can read data or
write data to memory or I/O ports either 16 bits
or 8 bits at a time.
• It has 20 address lines, so it can address up to
2^20 i.e. 1048576 = 1Mbytes of memory
(words i.e. 16 bit numbers are stored in
consecutive memory locations).
• Frequency range of 8086 is 6-10 MHz

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 Features Continued …
• 8086 includes few features, which enhance
multiprocessing capability (it can be used
with math coprocessors like 8087, I/O
processor 8089 etc.
• Operates on +5v supply and single phase
(single line) clock frequency.(Clock is
generated by separate peripheral chip 8284).
• 8086 comes with different versions. 8086
runs at 5 MHz, 8086-2 runs at 8 MHz, 8086-1
runs at 10 MHz.
• It comes in 40-pin configuration with HMOS
technology having around 20,000 transistors
in its circuitry.

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 Features Continued …
• It has multiplexed address and data bus
like 8085 due to which the pin count is
reduced considerably.
• Higher Throughput (Speed)(This is
achieved by a concept called pipelining).

Now a days 8086 is no longer used. But the

concept of its principles and structures is
very useful for understanding other
advanced Intel microprocessors

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 Pin Diagram of 8086

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 Internal Architecture of 8086

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 8086 Architecture Contd..
• 8086 has two blocks BIU (Bus Interface Unit) and
EU (Execution Unit).
• The BIU performs all bus operations such as
instruction fetching, reading and writing
operands for memory and calculating the
addresses of the memory operands. The
instruction bytes are transferred to the
instruction queue.
• EU executes instructions from the instruction
system byte queue.
• Both units operate asynchronously to give the
8086 an overlapping instruction fetch and
execution mechanism which is called as
Pipelining. This results in efficient use of the
system bus and system performance.

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 8086 Architecture Contd…

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 BUS INTERFACR UNIT: BIU
• It provides a full 16 bit bidirectional data
bus and 20 bit address bus.
• The bus interface unit is responsible for
performing all external bus operations.

Specifically it has the following

functions:
• Instruction fetch, Instruction queuing,
Operand fetch and storage, Address
relocation and Bus control.
• The BIU uses a mechanism known as an
instruction stream queue to implement a
pipeline architecture.
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 BIU Contd…
• This queue permits prefetch of up to six bytes of
instruction code. When ever the queue of the BIU
is not full, it has room for at least two more bytes
and at the same time the EU is not requesting it
to read or write operands from memory, the BIU
is free to look ahead in the program by
prefetching the next sequential instruction.
• These prefetching instructions are held in its FIFO
queue. with its 16 bit data bus, the BIU fetches
two instruction bytes in a single memory cycle.
• After a byte is loaded at the input end of the
queue, it automatically shifts up through the FIFO
to the empty location nearest the output.

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 BIU Contd…
• The EU accesses the queue from the output end. It
reads one instruction byte after the other from the
output of the queue.
• If the queue is full and the EU is not requesting
access to operand in memory. These intervals of
no bus activity, which may occur between bus
cycles are known as Idle state.
• If the BIU is already in the process of fetching an
instruction when the EU request it to read or write
operands from memory or I/O, the BIU first
completes the instruction fetch bus cycle before
initiating the operand read / write cycle.

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 BIU Contd.. Segment
registers
• 4 Segment registers in BIU are used to hold the
upper 16 bits of starting address of memory
• CS: is a 16-bit register containing address of 64
KB segment with processor instructions. The
processor uses CS segment for all accesses to
instructions referenced by instruction pointer
(IP) register. CS register cannot be changed
directly. The CS register is automatically
updated during far jump, far call and far return
instructions.

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 BIU Contd ….
• SS: is a 16-bit register containing address of 64KB
segment with program stack. By default, the
processor assumes that all data referenced by the
stack pointer (SP) and base pointer (BP) registers is
located in the stack segment. SS register can be
changed directly using POP instruction.
• DS: is a 16-bit register containing address of 64KB
segment with program data. By default, the processor
assumes that all data referenced by general registers
(AX, BX, CX, DX) and index register (SI, DI) is located
in the data segment. DS register can be changed
directly using POP and LDS instructions.

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 BIU Contd …
• ES: is a 16-bit register containing address of
64KB segment, usually with program data. By
default, the processor assumes that the DI
register references the ES segment in string
manipulation instructions. ES register can be
changed directly using POP and LES
instructions.
• Instruction Pointer (IP): is a 16-bit
register. It holds 16-bit address or offset of
the next code byte within code segment.

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 BIU Contd…
• The BIU also contains a dedicated adder which
is used to generate the 20bit physical address
that is output on the address bus. This address
is formed by adding an appended 16 bit
segment address and a 16 bit offset address.
• For example: The physical address of the
next instruction to be fetched is formed by
combining the current contents of the code
segment CS register and the current contents
of the instruction pointer IP register.
• The BIU is also responsible for generating bus
control signals such as those for memory read
or write and I/O read or write.

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 Execution unit
• The Execution unit is responsible for
decoding and executing all instructions.
• The EU extracts instructions from the top
of the queue in the BIU, decodes them,
generates operands if necessary, passes
them to the BIU and requests it to
perform the read or write bus cycles to
memory or I/O and perform the operation
specified by the instruction on the
operands.
• During the execution of the instruction,
the EU tests the status and control flags
and updates them based on the results of
executing the instruction.
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 Execution Unit Contd…
• If the queue is empty, the EU waits for the
next instruction byte to be fetched and
shifted to top of the queue.
• When the EU executes a branch or jump
instruction, it transfers control to a
location corresponding to another set of
sequential instructions.
• Whenever this happens, the BIU
automatically resets the queue and then
begins to fetch instructions from this new
location to refill the queue.

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 EU : Flag Registers
U U U U O D I T S Z U A U P U C
F F F F F F F F F
Undefine
8085 Compatible Flags
d
• OF : set if the result is too large positive number, or is too
small negative number to fit into destination operand.
• DF : String Direction Flag, if set then string manipulation
instructions will auto-decrement index registers. If cleared
then the index registers will be auto-incremented.
• IF : setting this bit enables maskable interrupts.
• TF : if set then single-step interrupt will occur after the
next instruction.
• SF : set if the most significant bit of the result is set.

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 EU : Flag registers…

• ZF : set if the result is zero.

• AF : Auxiliary Carry Flag, set if there was a
carry from or borrow to bits 0-3 in the AL
register.
• PF : Parity Flag, set if parity (the number
of "1" bits) in the low-order byte of the
result is even.
• CF : Carry flag, set if there was a carry
from or borrow to the most significant bit
during last result calculation.

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 EU Contd…: General Purpose
registers
• EU has eight general purpose
registersAH,AL,BH,BL,CH,CL,DH,DL
• These registers can be used to store 1 byte of
data
• AX is also called accumulator, Accumulator can
be used for I/O operations and string manipulation.
• Certain pairs of these GP regs can be used to
store 16-bit words ex. : AH/AL -> AX
BH/BL-> BX, CH/CL-> CX, DH/DL-> DX
• Advantage of using internal regs to store data is
that data can be accessed much more quickly

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 EU Contd…

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 EU Contd…
• Stack Pointer (SP) is a 16-bit register pointing to
program stack.
• Base Pointer (BP) is a 16-bit register pointing to data
in stack segment. BP register is usually used for
based, based indexed or register indirect addressing.
• Source Index (SI) is a 16-bit register. SI is used for
indexed, based indexed and register indirect
addressing, as well as a source data address in string
manipulation instructions.
• Destination Index (DI) is a 16-bit register. DI is
used for indexed, based indexed and register
indirect addressing, as well as a destination data
address in string manipulation instructions.

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 Memory Segmentation
• Memories of 8086: Program, data and
stack memories occupy the same memory
space.
• The total addressable memory size is 1MB.
As the most of the processor instructions
use 16-bit pointers the processor can
effectively address only 64 KB of memory.
• To access memory outside of 64 KB the
CPU uses special segment registers to
specify where the code, stack and data 64
KB segments are positioned within 1 MB of
memory.
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 Memory Segmentation

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 Memory Segmentation &
Addressing

The real mode memory-addressing scheme, using a segment

address plus an offset.
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 Memory Segmentation
Cont…
• 16-bit pointers and data are stored as:
address: low-order byte
address+1: high-order byte
• 32-bit addresses are stored in "segment:offset"
format as:
address: low-order byte of segment
address+1: high-order byte of segment
address+2: low-order byte of offset
address+3: high-order byte of offset
Physical memory address pointed by
segment:offset pair is calculated as:
address = (<segment> * 16) + <offset>
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 Generation of 20 bit physical
address
• The 20-bit Physical address is often
represented as, Segment Base : Offset
• OR CS : IP
CS 34800 Implied Zero
+IP 1234
-----------------------
3 5 A3 4 H

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 Microprocessor architecture
Contd..
• The programming model of the 8086
through the Pentium II
microprocessor.
• Some registers are general-purpose
or multipurpose registers, while
some have special purposes.

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 Programming Model

Figure 1.1
programmi
ng Model

Figure 1.1 The programming

model of the Intel 8086 through
the Pentium II.
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 Registers
• Registers hold various data sizes
(bytes, words, or doublewords) and
are used for almost any purpose as
dictated by a program.
• Multipurpose Registers
• Special-purpose Registers
• Segment Registers

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 Real mode memory
addressing
• Real mode operation allows the microprocessor
to address only the first 1M byte of memory
space - even the Pentium microprocessor.
• The first 1M byte of memory is called either the
real memory or conventional memory
system.
• Real mode operation allows application software
written for the 8088/8086, which contain only 1M
byte of memory, to function in the 80286 and
above without changing the software.
• In all cases, each of these microprocessors
begins operation in the real mode by default
whenever power is applied or the microprocessor
is reset.

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 Segments and offsets
• A combination of a segment address and
an offset address access a memory
location in the real mode.
• The segment address, located within one
of the segment registers, defines the
beginning address of any 64K-byte memory
segment.
• The offset address selects any location
within the 64K-byte memory segment.

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 Table 2.1 Example segment
addresses

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 Segments and offsets
• A 20-bit real mode address allows one to access the
start of a segment at any 16-byte boundary within
the first 1M byte of memory.
• Any real mode segments can only begin at a 16-byte
boundary in the memory system and this boundary is
often called a paragraph.
• In the 80286 (with special external circuitry) and the
80386 through the Pentium Pro, an extra 64K minus
16 bytes of memory is addressable when the
segment address is FFFFH and the HIMEM.SYS driver
is installed in the system.
• This area of memory (0FFFF0H-10FFEFH) is referred
to as high memory.

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 Default segment and offset
registers
• The microprocessors has a set of rules
that apply to segments whenever
memory is addressed.
• These rules, which apply in either the
real or protected mode, define the
segment register and offset register
combination used by certain
addressing modes.

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 Default Segment and Offset
Registers

8086-80486 and Pentium-Pentium II default 16-bit segment

and offset address combinations.

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 Default segment and offset
registers
• The code segment register defines the
start of the code segment and the
instruction pointer locates the next
instruction within the code segment.
• Stack data are references through the
stack segment at the memory location
addressed by either the stack pointer
(SP/ESP) or the base pointer (BP/EBP).

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 Default Segment 7 Offset
registers

80386, 80486, Pentium, Pentium Pro, and Pentium II default 32-bit segment and
offset address combinations.

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 Default segment and offset
registers
• One can think of segments as windows
that can be moved over any area of
memory to access data and code.
• A program can have a lot of segments,
but can only access four (in 8086-
80286) or six (in 80386 and above)
segments at a time.

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 Addressing Modes
• Immediate Addressing: the data is provided in the
instruction, MOV CX, 437AH
• Direct Addressing (Segment Override prefix): the
instruction operand specifies the memory address where
data is located, MOV BL, [437AH]
• Register Addressing: references the data in a register or in
a register pair, MOV CS, AX
• Register Indirect Addressing : instruction specifies a
register containing an address, where data is located. This
addressing mode works with SI, DI, BX and BP registers.

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 Tutorial
Q1. Describe the sequence of signals that occurs
on the address bus, the control bus and the
data bus when a simple microcomputer fetches
an instruction?
A1. The Sequence of signals is as follows:
- Address is sent out on address bus
- Memory read signal is sent out on control bus
- Memory sends instruction byte/s on data bus
- CPU reads in the instruction and decodes it

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 Tutorial Contd ….
Q2. What is the main difference
between 8086 and 8088?

A2. The 8088 has an 8-bit data bus , so

it can write to or read from memory,
ports only 8-bits at a time. The 8086
can read/write 8-bit or 16-bits at a
time

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 Tutorial Contd…
Q3. What physical address is
represented by
a.4370:561EH
b.7A32:0028H

A3. 4370:5610H is equivalent to

43700H+561EH= 48D1EH
7A32:0028H is equivalent to
7A320H+0028H= 7A348H

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 Tutorial Contd…
Q4. Write the 8086 asembly language statement
which will perform the following operations
a. Load the number 7986H into the BP register
b. Copy the BP register contents to the SP register
c. Copy the contents of the AX register to the DS
register
d. Load the number F3H into the AL register ?

A4.
a. MOV BP, 7986H
b. MOV SP, BP
c. MOV DS, AX
d. MOV AL, F3H

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 Tutorial Contd…
Q5. Describe the difference between
the instructions MOV AX, 2437H and
MOV AX, [2437H] ?
A5. MOV AX,2437H: loads the AX
register with no. 2437H.
MOV AX,[2437H]: loads the contents of
memory location DS+2437H into AL
and DS+2437H+1 into AH register

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 Intel 80286 Microprocessor
• The major new feature of the 80286 microprocessor
was protected mode. When switched to this mode, the
CPU could address up to 16 MB of operating memory
(previous generation of 8086/8088 microprocessors was
limited to 1 MB).
• In the protected mode it was possible to protect
memory and other system resources from user
programs - this feature was necessary for real program
multitasking. While this mode was useful for
multitasking operating systems, it was of limited use for
systems that required execution of existing x86
programs. The protected mode couldn't run multiple
virtual 8086 programs.

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 Intel 80286 Contd..
• 80286 was a 16-bit microprocessor.
Although in protected mode the CPU
could address up to 16 MB of
memory, this was implemented using
memory segments. Maximum size of
memory segment was still 64 KB.
• There was no fast and reliable way to
switch back to real mode from
protected mode.

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 Intel 386 Microprocessor
• It is an entry-level 32-bit microprocessor designed
for single-user applications and operating systems
such as MS-DOS and Windows.
Base Architecture the Intel 386 consists of three
major components:
• a central processing unit (CPU)
• a memory management unit
-- segmentation unit
-- the paging mechanism
the Intel has two modes of operation: Real Address
Mode (Real Mode), and Protected Virtual Address
Mode (Protected Mode).
• a bus interface
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 Intel 80386 Contd..
• The 80386 mode included complete set of 32-bit
registers and 32-bit instructions.
• Although in this mode the CPU still used memory
segment architecture similar to the one present
in earlier x86 microprocessors, the size of
memory segments was increased to 4 GB. This
simplified development of 32-bit software, and in
most cases applications could run without
worrying about switching memory segments.
• It became possible to switch from protected
mode back to real-mode without simulating
processor reset.

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 Intel 80386 Contd..
• Another new mode in the 80386 CPU was
8086 virtual mode. In this mode the CPU
could run old 8086 applications while
providing necessary protection of
memory and other resources.
Introduction of this mode and 80386
protected mode was very significant step.
All current 32-bit x86-based operating
systems use these modes to run legacy
16-bit and more modern 32-bit
applications.

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 Intel 486 microprocessor
The Intel 486 CPU offers the highest performance for DOS,
OS/2, Windows, and UNIX system V/Intel 386 applications. Its
100% binary compatible with the Intel 386 CPU.

• Real Mode Architecture.

• Protected Mode Architecture
• On-Chip Cache

• 8 KB unified level 1 cache for code

and data was added to the CPU. In
later versions of the 80486 the size of
level 1 cache was increased to 16 KB.

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 Intel 80486 Contd..
• Execution time of instructions was significantly
reduced. Many load, store and arithmetic
instructions executed in just one cycle (assuming
that the data was already in the cache).
• Intel 486 featured much faster bus transfers - 1
CPU cycle as opposed to two or more CPU cycles
for the 80386 bus.
• Floating-point unit was integrated into 80486DX
CPUs. This eliminated delay in communications
between the CPU and FPU. Furthermore, all
floating-point instructions were optimized - they
required fewer number of CPU cycles to execute.

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 Intel 80486 Contd..
• Clock-doubling and clock-tripling technology was
introduced in faster versions of Intel 80486 CPU.
These i486 processors could run in existing
motherboards with 20 - 33 MHz bus frequency,
while running internally at two or three times of
bus frequency. 80486SX2 and 80486DX2 were
clock-doubled version, and 80486DX4 was a
clock-tripled version. AMD also produced
80486DX5 or X5 - clock-quadrupled version of the
80486.
• Power management features and System
Management Mode (SMM) became a standard
feature of the processor.

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