VLSI Interconnects

Instructed by Shmuel Wimer

Eng. School, Bar-Ilan University

Credits: David Harris

Harvey Mudd College
(Some material copied/taken/adapted from
Harris lecture notes)
Dec 2010

VLSI Interconnects

Outline
Introduction
Wire Resistance
Wire Capacitance
Wire RC Delay
Crosstalk
Wire Engineering
Repeaters
Scaling
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VLSI Interconnects

Introduction
Chips are mostly made of wires called interconnect
Alternating layers run orthogonally

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VLSI Interconnects

 Transistors are little things under the wires

Many layers of wires

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VLSI Interconnects

 Wires are as important as transistors

Speed
Power
Noise

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VLSI Interconnects

Wire Geometry
Pitch = w + s
Aspect ratio: AR = t/w
Old processes had AR << 1
Modern processes have AR 2
Pack in many skinny wires

t
h

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VLSI Interconnects

Layer Stack
Modern processes use 6-10+ metal layers
Example: Intel 180 nm process
M1: thin, narrow (< 3)
High density cells
M2-M4: thicker
For longer wires
M5-M6: thickest
For VDD, GND, clk

Layer

T(nm)

W(nm) S (nm)

AR

1720

860

860

2.0

1600

800

800

2.0

1080

540

540

2.0

700

320

320

2.2

700

320

320

2.2

480

250

250

1.9

Substrate
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VLSI Interconnects

Wire Resistance
= resistivity (*m)

l
l
R
RW
t w
w

R = sheet resistance (/)

is a dimensionless unit(!)
Count number of squares
R = R * (# of squares)

l
w

t
1 Rectangular Block
R = R (L/W)

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VLSI Interconnects

4 Rectangular Blocks
R = R (2L/2W)
= R (L/W)

Choice of Metals
Until 180 nm generation, most wires were aluminum
Modern processes use copper
Cu atoms diffuse into silicon and damage FETs
Must be surrounded by a diffusion barrier
Metal

Bulk resistivity (*cm)

Silver (Ag)

1.6

Copper (Cu)

1.7

Gold (Au)

2.2

Aluminum (Al)

2.8

Tungsten (W)

5.3

Molybdenum (Mo)

5.3

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VLSI Interconnects

Sheet Resistance
Typical sheet resistances in 180 nm process
Layer

Sheet Resistance (/)

Diffusion (silicided)

3-10

Diffusion (no silicide)

50-200

Polysilicon (silicided)

3-10

Polysilicon (no silicide)

50-400

Metal1

0.08

Metal2

0.05

Metal3

0.05

Metal4

0.03

Metal5

0.02

Metal6

0.02

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VLSI Interconnects

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Contacts Resistance
Contacts and vias also have 2-20
Use many contacts for lower R
Many small contacts for current crowding around
periphery

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Wire Capacitance
Wire has capacitance per unit length
To neighbors
To layers above and below
Ctotal = Ctop + Cbot + 2Cadj
s

w
layer n+1

h2

Ctop

t
h1

Cbot

Cadj

layer n

layer n-1

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Capacitance Trends
Parallel plate equation: C = A/d
Wires are not parallel plates, but obey trends
Increasing area (W, t) increases capacitance
Increasing distance (s, h) decreases capacitance
Dielectric constant
= k0
0 = 8.85 x 10-14 F/cm
k = 3.9 for SiO2
Processes are starting to use low-k dielectrics
k 3 (or less) as dielectrics use air pockets
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M2 Capacitance Data
Typical wires have ~ 0.2 fF/m
Compare to 2 fF/m for gate capacitance
400

300

M1, M3 planes
s = 320

Capacitance decreases
with spacing

250

s = 480
s=

200

s = 640
Isolated
s = 320

150

s = 480
s = 640
s=

100

Ctotal (aF/ m)

Capacitance increases
with metal planes
above and below

350

50

0
0

500

1000

1500

2000

w (nm)

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Diffusion & Polysilicon

Diffusion capacitance is very high (about 2 fF/m)
Comparable to gate capacitance
Diffusion also has high resistance
Avoid using diffusion (and polysilicon) runners for
wires!
Polysilicon has lower C but high R
Use for transistor gates
Occasionally for very short wires between gates
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VLSI Interconnects

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Lumped Element Models

Wires are a distributed system
Approximate with lumped element models
N segments
R

R/N

R/N

C/N

C/N

R
C
L-model

C/2

R/N

R/N

C/N

C/N

R/2 R/2
C/2

-model

C
T-model

3-segment -model is accurate to 3% in simulation

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RC Example
Metal2 wire in 180 nm process
5 mm long
0.32 m wide
Construct a 3-segment -model
=> R = 781
R = 0.05 /
Cpermicron = 0.2 fF/m

=> C = 1 pF

260

260

260

167 fF 167 fF

167 fF 167 fF

167 fF 167 fF

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Wire RC Delay Example

Estimate the delay of a 10x inverter driving a 2x
inverter at the end of the 5mm wire from the
previous example
R = 2.5 k*m for gates
Unit inverter: 0.36 m nMOS, 0.72 m pMOS
781
690

tpd = 1.1 ns
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Driver

500 fF 500 fF
Wire

VLSI Interconnects

4 fF
Load
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Crosstalk
A capacitor does not like to change its voltage
instantaneously
A wire has high capacitance to its neighbor.
When the neighbor switches from 1 0 or 0 1,
the wire tends to switch too.
Called capacitive coupling or crosstalk
Crosstalk effects
Noise on non switching wires
Increased delay on switching wires
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VLSI Interconnects

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Miller Effect
Assume layers above and below on average are quiet
Second terminal of capacitor can be ignored
Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors
Miller effect
B

Ceff(A)

MCF

Constant

VDD

Cgnd + Cadj

Cgnd

Switching with 0
A
Switching
opposite A
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2VDD Cgnd + 2 Cadj

VLSI Interconnects

Delay and power

increase

A
C gnd

B
C adj

C gnd

23

Crosstalk Noise
Crosstalk causes noise on non switching wires
If victim is floating:
model as capacitive voltage divider

Vvictim

Cadj
Cgnd-v Cadj

Vaggressor

Aggressor
Vaggressor

Cadj
Victim
Cgnd-v

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Vvictim

VLSI Interconnects

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Driven Victims
Usually victim is driven by a gate that fights noise
Noise depends on relative resistances
Victim driver is in linear region, agg. in saturation
If sizes are same, Raggressor = 2-4 x Rvictim
Vvictim

Cadj

Vaggressor
Cgnd-v Cadj 1 k

aggressor
victim

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Raggressor Cgnd-a Cadj

Rvictim Cgnd-v Cadj

Raggressor
Cgnd-a

Vaggressor

VLSI Interconnects

Aggressor
Cadj

Rvictim

Victim
Cgnd-v

Vvictim

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Coupling Waveforms
Simulated coupling for Cadj = Cvictim
Aggressor

1.8

1.5

1.2

Victim (undriven): 50%

0.9

0.6

Victim (half size driver): 16%

Victim (equal size driver): 8%

0.3

Victim (double size driver): 4%

0
0

200

400

600

800

1000

1200

1400

1800

2000

t (ps)

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Noise Implications
So what if we have noise?
If the noise is less than the noise margin, nothing
happens
Static CMOS logic will eventually settle to correct
output even if disturbed by large noise spikes
But glitches cause extra delay
Also cause extra power from false transitions
Dynamic logic never recovers from glitches
Memories and other sensitive circuits also can
produce the wrong answer
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Wire Engineering

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 Goal: achieve delay, area, power goals with

acceptable noise
Degrees of freedom:
Width
Spacing
Layer
Shielding

vdd a0

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a1 gnd a2

a3 vdd

vdd a0 gnd a1 vdd a2 gnd

VLSI Interconnects

a0

b0

a1

b1

a2

b2

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Repeaters
R and C are proportional to l
RC delay is proportional to l2
Unacceptably great for long wires
Break long wires into N shorter segments
Drive each one with an inverter or buffer
Wire Length: l
Driver

Receiver
N Segments
Segment
l/N

Driver

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l/N
Repeater

l/N
Repeater

Repeater

VLSI Interconnects

Receiver

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Repeater Design
How many repeaters should we use?
How large should each one be?
Equivalent Circuit
Wire length l
Wire Capacitance Cw*l, Resistance Rw*l
Inverter width W (nMOS = W, pMOS = 2W)
Gate Capacitance C*W, Resistance R/W
Rwl/N
R/W

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Cwl/2N Cwl/2N
VLSI Interconnects

C'W
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Showing that repeater insertion pays

w/o repeater k=1

1.21RoCo Ri Ci 0.16 Ri 2Ci 2 0.56 RoCo Ri Ci 0.49 Ro 2Co 2

0 0.16 Ri 2Ci 2 0.65 RoCo Ri Ci 0.49 Ro 2Co 2

0 0.4 Ri Ci 0.7 RoCo 0.09 RoCo Ri Ci

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VLSI Interconnects

small

33

Under what condition repeater insertion should take place?

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Cascaded driver with non-repeated interconnect

Non-repeated interconnect

The method is useful when Rtr is dominant and Cint is large

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Optimal Buffer Insertion

v
?

u,q
u,q
d v, ui : driver to receiver delay. Root required time: T min qi d v, ui .
i

Buffer reduces load delay but adds internal delay, power and area.
Problem 1:

max

buffer insertions

Problem 2:

max

min q d v, u by buffer insertion at internal nodes.

min q d v,u , s.t. power and area constraints.

buffer insertions

39

Delay Model
d v, ui R jiC j R j L j
j
j i

R4
C4

R2
2
C3

R5

R1

5
C5

1
R6

C1
R3
C2

T k - nodes of sub-tree rooted at node k

6
C6

k - nodes along path from root to node k

R7

7
C7

Rkl j k I l R j - resistance along common paths

Lk jT k C j - capacitance of sub-tree
40

Bottom-Up Solution
TK min TM , TN
LK LM LN

sub-tree
(TM , LM)
(TK , LK)

(TK , LK)
RK

without buffer
1
TK TK RK LK RK CK
2
LK LK CK

RM

CM

K
sub-tree

CK
RN
(TN , LN)

CN

with buffer
TK TK Dbuffer Rbuffer LK RK Cbuffer

1
RK CK
2

LK Cbuffer CK
41

Scaling

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Scaling

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